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UNITED STATES

SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

FORM 10-K

(Mark one)

For the Fiscal Year Ended December 31, 2004

For The Transition Period From                  To                 

Commission File Number: 0-21626

Electroglas, Inc.

(Exact Name of Registrant as Specified in its Charter)

Securities registered pursuant to Section 12(b) of the Act: None

Securities registered pursuant to Section 12(g) of the Act:

Common Stock, $0.01 par value

(Title of Class)

Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.    Yes x    No ¨

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K.    x

Indicate by check mark whether the registrant is an accelerated filer (as defined in Exchange Act Rule 12b-2).    Yes x    No ¨

As of June 30, 2004, the aggregate market value of the voting and non-voting common equity held by non-affiliates of the Registrant was approximately $116,011,000, based on the closing sale price as reported on the Nasdaq National Market on such date. This calculation does not reflect a determination that certain persons are affiliates of the Registrant for any other purposes.

As of March 8, 2005, the Registrant had 21,954,320 outstanding shares of Common Stock.

DOCUMENTS INCORPORATED BY REFERENCE

Portions of the Registrant’s Proxy Statement in connection with the Annual Meeting of Stockholders, to be held on May 26, 2005, are incorporated by reference into Part III of this Form 10-K.

Table of Contents

ELECTROGLAS, INC.

FORM 10-K

For the Year Ended December 31, 2004

INDEX

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FORWARD LOOKING STATEMENTS

The discussion in this Annual Report on Form 10-K should be read in conjunction with our accompanying Financial Statements and the related notes thereto. This Annual Report on Form 10-K and certain information incorporated herein by reference contain forward looking statements within the “safe harbor” provisions of the Private Securities Litigation Reform Act of 1995, Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Exchange Act, as amended. All statements included or incorporated by reference in this Annual Report, other than statements that are purely historical, are forward-looking statements. Words such as “anticipates,” “expects,” “intends,” “plans,” “believes,” “seeks,” “estimates” and similar expressions also identify forward looking statements. These forward looking statements are not guarantees of future performance and are subject to risks and uncertainties that could cause actual results to differ materially from the results contemplated by the forward looking statements and include, without limitation, statements regarding:

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The forward looking statements are subject to risks and uncertainties that could cause actual results to differ materially from those stated or implied by the forward looking statements. These risks and uncertainties include:

For a detailed description of these and other risks associated with our business that could cause actual results to differ from those stated or implied in such forward-looking statements, see the disclosure contained under the heading “Factors that May Affect Results and Financial Condition” in this Annual Report on Form 10-K. All forward looking statements included in this document are made as of the date hereof, based on information available to us as of the date hereof, and we assume no obligation to update any forward looking statement or statements. The reader should also consult the cautionary statements and risk factors listed in our Reports on Forms 10-K, 10-Q, 8-K and other reports filed from time to time with the Securities and Exchange Commission.

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PART I

Item 1.    Business

Overview

We are a supplier of semiconductor manufacturing equipment and software to the global semiconductor industry. We were incorporated in Delaware on April 1, 1993, to succeed the wafer prober business conducted by the Electroglas division of General Signal Corporation, our former parent. Immediately prior to the closing of the initial public offering of our Common Stock, or IPO, on July 1, 1993, we assumed the assets and liabilities of the Electroglas division in the asset transfer. Following our IPO, we commenced operations as an independent corporation. We, through our predecessors, have been in the semiconductor equipment business for more than 40 years.

Our primary product line is automated wafer probing equipment and related network software to manage information from that equipment. In conjunction with automated test systems from other suppliers, our semiconductor manufacturing customers use our wafer probers and network software to quality test semiconductor wafers and to improve their productivity and control their processes, optimizing manufacturing efficiency. Electroglas’ installed base is one of the largest in the industry, having sold over 15,000 wafer probers.

Introduced in 2004, the 4090µ+ addresses the demands of testing fine pitch devices, semiconductors with copper interconnects and low-k dielectric processes and other advanced applications, while simultaneously reducing test costs by increasing test cell availability and throughput.

In January 2001, we acquired Statware Inc., of Corvallis, Oregon, to further expand our network software product offerings in the test management area. Today, the Statware technology is the basis for our web-based applications that allow our customers to monitor and control probers from any location, as well as collect, analyze, and report critical test process information and automatically direct corrective action.

We are also involved in the development, manufacture, marketing, and servicing of test handlers as part of our strategy to be a comprehensive semiconductor test solutions provider. Built upon our proven prober technology, the test handlers expand available markets by providing solutions to the final test segment for today’s latest packaging technologies and test processes. This includes Wafer Level Packages (WLP), Known-Good Die (KGD), Microelectromechanical Systems (MEMS), ultra-thin and/or diced wafers. It also includes many package tested strip formats, whether panel or leadframe such as Chip Scale Packages (CSP) or Ball Grid Arrays (BGA) as well as traditional Small Outline Integrated Circuits (SOIC).

Starting in 2003, we set our focus on our core competency in wafer probing, delivering advanced wafer probers and extending our wafer probing technologies to drive equipment and process efficiencies throughout the back-end of the semiconductor manufacturing process. This included the sale of Fab Solutions software product lines and our Optical Inspection product line. Our renewed focus allowed us to spend more time developing and delivering innovative products to help our customers overcome their most critical semiconductor test challenges. In 2004, this resulted in the introduction of a new extended performance 200mm wafer prober, the 4090µ+, and the development of a new flagship 300mm prober, the EG6000, introduced in January 2005 that represents a major advancement in prober design and automation and is focused on providing substantially better performance than currently available competitor’s products.

Additional information about Electroglas is available on our web site at www.electroglas.com. Electroglas makes available free of charge on our website our Annual Reports on Form 10-K, our Quarterly Reports on

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Form 10-Q, our Current Reports on Form 8-K and amendments to those Reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, as amended, as soon as reasonably practicable after we electronically file them with or furnish them to the Securities Exchange Commission. The public may read and copy any materials that we file with the SEC at the SEC’s Public Reference Room at 450 Fifth Street, N.W., Washington, D.C. 20549. The public may obtain information on the operation of the Public Reference Room by calling the SEC at 1-800-SEC-0330. Our Annual Reports on Form 10-K, our Quarterly Reports on Form 10-Q and other filings also are available at the SEC’s website at http://www.sec.gov.

Industry Background

Semiconductor devices are fabricated by repeating a complex series of process steps on a substrate, or wafer, which is usually made of silicon. Wafers are typically sent through a series of 100 to 400 process steps. A finished wafer consists of many integrated circuits, each referred to as a “device” or “die” or “chip”, the number of which depends on the area of the circuits and the size of the wafer. These wafers measure from 75mm to 300mm, or 3 to 12 inches, in diameter. Manufacturers have increasingly utilized larger diameter wafers to achieve more cost-effective production. The move to 300mm (12-inch) wafers, a significant trend for equipment manufacturers, began in 2000.

The manufacture of semiconductor devices is very capital intensive. A typical state of the art facility, usually called a “wafer fab”, can cost more than $2 billion. The purchase of semiconductor manufacturing equipment and spare parts, the integration of such equipment into production lines, and the training of employees on a particular supplier’s equipment require significant expenditures by semiconductor manufacturers.

Wafer Probing

A wafer prober successively positions each die on the wafer so that the electrical contact points, or pads, on the die align under and make contact with probe pins, which are located on a probe card mounted on the wafer prober. The probe card, which is generally custom-made by other suppliers for the specific device being tested, is

Wafer probing requires sophisticated machine vision and software capabilities to align each die on a wafer — often to accuracies as tight as 2.5µm — to pins on a probe card connected to a tester that measures electrical performance.

connected to a test system, also supplied by other suppliers, which performs the required parametric or functional test. Parametric testing is performed during the wafer fabrication process, referred to as “in-line testing,” and at the completion of the wafer fabrication process, referred to as “end-of-line testing,” to measure electrical parameters that verify the reliability of the wafer fabrication process. Functional testing is performed after the completion of wafer fabrication to identify devices that do not conform to particular electrical specifications or performance criteria. This process is commonly called “wafer sort.” Wafers often go through several wafer probing steps during the manufacturing process.

Automatic wafer probers are primarily used during this “wafer sort” process, which occurs after the fabrication steps are completed and before the separation and packaging of each individual device. Positioning accuracy is a key requirement of an automatic wafer prober. As manufacturers continue to shrink their device sizes, the manufacturing equipment accuracy must continue to keep pace with reduced feature sizes. Throughput is another key prober feature, because allowing more devices to be tested in a given amount of time reduces the overall cost of test. Similarly, wafer probers are required to be reliable, easy to use, and very robust at handling the test process without failure or interruption, since these cause loss of throughput for the entire test cell.

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Recently, new device manufacturing processes, such as the use of copper for the metal layers and the use of very soft, delicate dielectric layers, have required a new level of control over the speed and accuracy with which probes are brought into contact with the pads to prevent damage and yield loss.

Wafer probers are also used during in-line parametric testing. In-line testing requires special equipment features such as cleanroom compatibility and low-noise electrical measurement capability, as tests are carried out during the fabrication process. This testing is done to verify the quality of the manufacturing process while wafers are in an unfinished state where corrective action can occur. A small number of probers are also used for research and development, and quality and process control applications. We estimate based upon our experience that wafer sort applications represent as much as 85% of the market for automatic wafer probers. The remaining 15% is divided between in-line and end-of-line testing and laboratory applications.

There is a growing trend for semiconductor manufacturers to contract with other companies to perform their wafer sort operations. These contract test companies, commonly called “test houses”, perform the wafer testing service and often provide assembly and packaging services as well.

A semiconductor manufacturer typically purchases wafer probers when outfitting a new wafer fabrication facility or expanding an existing facility. Wafer probers are also purchased to replace equipment in response to major changes in technology such as larger wafer sizes and greater device complexity. A semiconductor fabrication facility may require from 20 to over 100 probers to meet testing requirements on a timely basis. A test house may require hundreds of wafer probe systems to support the testing requirements of the companies that contract with them.

Test Handling

Wafers are sent from the wafer sort operation to assembly where the individual chips are separated with wafer saws, and put into protective packages. Once packaged, chips are tested again to make sure they function properly before being shipped to a customer. Ultimately, these packaged chips will find their way into electronic systems that go into a myriad of familiar consumer and industrial electronic applications.

For traditional packages, the desire to reduce the cost of assembly and test has chipmakers looking for ways to increase test efficiency. As demand continues to grow for the highest volume leadframe-based packages, such as SOIC’s, there is an increasing need to find new test methods to improve test throughput and lower the cost of test.

In addition, a revolution in semiconductor packaging is currently being driven by the trend to shrink the size and weight of consumer electronics devices, such as mobile phones, personal digital assistants (PDA’s), and notebook computers, while increasing performance. This has caused the advent of very small packages which have made it increasingly difficult to handle devices individually. Manufacturers and test houses are looking for new and more efficient methods to handle these types of packages.

One of the primary new technologies for meeting these needs is the strip test handler which enables testing devices while in strip or panel format. By performing test while devices are held in position on these strips, strip test handlers allow small high-speed devices to be accurately positioned and numerous devices can be tested and handled simultaneously. Because it handles packaged devices in the matrix format of the strip, a strip test handler has many similarities to a wafer prober, which handles chips in the matrix format of a wafer.

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Packaging trends provide new opportunities for Electroglas as final test becomes more like wafer test with large arrays of devices on a substrate, very small package size and contacts, and a need for higher levels of test parallelism to drive down costs.

The Electroglas strip test handler, Sidewinder, uses prober technology and unique machine vision and handling methodology to deliver the fastest possible strip-to-strip index time available.

Another trend is the increasing number of devices that are being shipped from device manufacturers as Known Good Die (KGD), that is, bare die, without any packaging. These devices are commonly shipped by the device manufacturers to customers who assemble multi-chip modules or mount them directly to circuit boards. In this application, the bare die is the final “package” for the device manufacturer. Also, semiconductor manufacturers are increasingly using stacked packages to combine two or more chips of differing technologies into a single package. In either of these applications, it is often necessary to test individual chips after devices have been separated on a wafer saw. A film frame handler allows this type of		The Electroglas film-frame handler, Pathfinder, allows testing of devices after dicing using advanced software algorithms that correct for die placement inaccuracies resulting from singulation.
testing to be done while the devices are still mounted on the film (which is held in place by a round metal or plastic frame) used for the wafer sawing process.

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Test Floor Management

Process management software plays an important role in Integrated Circuit (IC) manufacturing. Capital and operating costs of a fabrication facility are very high so semiconductor manufacturers are seeking ways to improve overall equipment efficiency (OEE) and optimize their processes. Test houses and Integrated Device Manufacturers look to reduce the cost of test and improve quality through software monitoring, analysis, and the automation of their test floors.

In a wafer sort area, network software is increasingly being used to manage wafer information to speed the identification of yield shortfalls and reduce reprobe rates by collecting wafer maps from multiple passes for all systems and storing the files in a common database for viewing, analyzing and archiving. Other uses include prior step verification to insure that wafers will accurately flow through a pre-defined set of steps and will not be tested if they have not completed the previous step in the process and, product file management capabilities that allow the user to save a master template for product file set-up that can be accessed by all test systems on the test floor.

In general, software tools are used to bring together disparate data to automate and optimize the operational efficiency of the semiconductor fabrication facility. The software provides a common location and format for presenting this data and doing cross-correlation between data types for the purpose of overall equipment efficiency analysis and, ultimately, manufacturing process optimization.

Our Strategy

We are a major supplier of wafer probers due to a combination of strengths, including a large installed base, advanced technical capabilities, close relationships with the leading manufacturers of integrated circuits, a broad

From the sort floor to final test, Electroglas’ hardware and software enable chipmakers to collect, share, analyze and act on essential semiconductor test data — saving significant time, increasing yields and improving profitability.

line of high quality products, and a well-established, highly qualified distribution organization. Building on these capabilities, our strategy is comprised of the following key elements:

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Products

Wafer Probers

Horizon 4000 Series:    The 4090µ+ (4090 Micro Plus) was introduced in Q4 2004 and is the new extended performance wafer prober system for 200mm wafers. The 4090µ+ addresses the demands of testing fine pitch devices, semiconductors with copper interconnects and low-k dielectric processes, and other advanced applications. Employing MicroTouch, a feature that decreases the impact force as the probe pins contact the bond pads, the 4090µ+ reduces touchdown damage that can occur when testing fragile copper and low k devices or when pads are located over active circuit geometry. The 4090µ+ increases test cell availability and throughput while simultaneously reducing test cost by making improvements in how probe-to-pad alignment is maintained in varying temperature environments. In addition, the 4090µ+ has simplified and fully automated operations for high volume manufacturing applications, such as those that exist in integrated device manufacturer (IDM) and contract test facilities. Customers who want to use the latest high productivity 200mm probing solution from Electroglas can also cost-effectively upgrade existing Electroglas 4080, 4090 and 4090µ prober systems with 4090µ+ technology. Joining the 4090u+ in the Horizon 4000 Series is the 4090µ Fast Probe, introduced in 2001, which is used in applications where the die are very small and there is a very large number of devices on a wafer. The 4090µ Fast Probe employs special technologies to reduce the system stepping time for high-volume production.

The EG4/200:    Introduced in 1999, the EG4|200 is targeted at high-end probing applications for 200mm wafers. The system utilizes a unique “probe-centered z-drive” to provide very low deflections, even under extremely high probe forces. This is important when testing multi-site or high pin count devices. The EG4|200 retains many of the features of the Horizon 4000 series probers such as a linear motor and an air-bearing positioning system.

The EG6000:    Developed in 2004 and introduced in January 2005, the new EG6000 300mm probing system from Electroglas fuses advanced automation with the highest caliber of prober technology. Representing a major advancement in prober design and automation, the system is the only 300mm prober that employs precision direct-drive technology to enable it to achieve the highest positioning accuracy currently available. Simultaneously, the prober can deliver the fastest throughput obtainable as measured from lot-start to lot-end. Designed for advanced applications such as copper and low k dielectrics, the system employs a proprietary stage and control technology to enable highly accurate positioning of the test devices while moving devices into contact with the probes for test. MicroTouch adds the ability to control the impact forces while probing on delicate devices. The EG6000 features the new Advanced Vision System for better accuracy, robustness and speed in aligning devices to the probe card for test. It also features a sophisticated system for automatically measuring and compensating for thermal changes in the system components while testing at hot or cold temperatures.

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The EG6000 is based on the same core architecture as the prior 5|300 prober which served the relatively small market for parametric test and process development applications. The EG6000 features a broader range of application capabilities as well as many refinements and improvements in accuracy, throughput, automation, and reliability. This allows the EG6000 to address customer’s needs for high volume production wafer test that forms the large majority of the 300mm prober market.

Parametric Probers:    The EG5|300e, introduced in December 2000, and the EG4|200e, introduced in July 2001, are both targeted at the parametric test (“e-test”) segment of the wafer probe market. The EG5/300e is targeted at the 300mm market. The EG4|200e, based on the EG4|200 platform, addresses the 200mm market. Both systems incorporate patented technology licensed from our partner, Cascade Microtech, Inc. This technology allows extremely precise, low-level electrical measurements to be made at the wafer level. This type of electrical measurement performance is becoming increasingly critical for advanced sub-micron semiconductor processes.

Test Handlers

Pathfinder:    Introduced in 2002, the Pathfinder system is designed to meet the unique test handling requirements of the Known Good Die (KGD) and Wafer Level Package (WLP) markets. The Pathfinder system features a unique material handling system that can handle and position wafers and packages on a film frame after they have been sawn (“diced”). Special alignment techniques are used to compensate for the variability inherent in these sawn wafers and packages. Because it handles wafers while supported by a film frame,

Sidewinder leverages Electroglas’ proven prober technology to deliver superior throughput and accuracy for final test handling of packaged semiconductor and discrete components in panel or lead frame format.

Pathfinder is also capable of handling ultra-thin wafers.

Sidewinder:    Introduced in 2003, Sidewinder provides final test handling of packaged semiconductor and discrete components in panel or lead frame format. Termed “strip testing”, Sidewinder’s technology enables the handling of fine geometry packages such as chip scale packages (CSP) that are difficult to test in singulated format, and higher parallel test capability for small outline package (SOP), quad flat no-lead (QFN), and other well established high volume packages. The first strip test handler to be based on advanced 300mm prober technology, Sidewinder, combines Electroglas’ proven prober stage with a sophisticated machine vision-based alignment system that offers improved accuracy and system throughput. Sidewinder’s market is comprised of companies who need technology that enables them to test advanced devices in new packages, as well as companies seeking increased efficiency in testing traditional packages in panel or lead format. In 2004, Sidewinder was selected by Advanced Packaging, a leading semiconductor publication, as a 2004 Advanced Packaging Award Winner based on its ability to meet a significant industry challenge, creative application of technology; and throughput characteristics.

Test Floor Management Software Products

From the sort floor to final test, Electroglas’ software enables chipmakers to collect, share, analyze and act on essential data—saving time and helping to improve profitability.

The answers to chipmakers most pressing questions lie in the multitude of data that are generated from their manufacturing processes. Unfortunately, that information is often not easily accessible, making it difficult for engineers and managers to act upon the most recent critical data. Electroglas helps manufacturers overcome this knowledge gap and attain faster answers to questions about their productivity, offering software solutions that provide insight into the manufacturing process.

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SORTmanager displays single and composite wafer maps and underlying data for custom views of multiple lots that enable users to make the most effective comparison possible for identification and rapid resolution of process issues to correct yield loss.

SORTmanager:    Bridging the gap between raw data and genuine process improvement is the difference between data overload and real productivity gains. Electroglas’ SORTmanager provides that bridge, enabling a secure, web-based environment for the analysis, reporting and control of sort-floor processes. Data about test results, binning, prober performance and throughput can be collected from all SORTmanager-connected wafer probers, and that information can then be delivered via dynamic, interactive web pages that allow users to view the underlying data or perform additional analysis. Powerful web publishing capabilities allow web reports to be created and distributed throughout an enterprise. SORTmanager’s flexible data-access and information viewing capabilities, combined with a comprehensive suite of pre-built applications and a scripting language for fine tuning applications to customer needs, makes SORTmanager a unique and powerful test floor management tool.

Engineering, Research and Development

The market for semiconductor manufacturing equipment is characterized by continuous technological development and a high rate of product innovation. We believe that continued, rapid development of new products and enhancements to existing products is necessary to maintain our competitive position. For example, we devote a significant portion of our personnel and financial resources to engineering, research and development programs for our wafer prober product line to continue a high level of development for 200mm wafer probers as well as to develop an entirely new platform for 300mm wafer probers. In addition, we continue to invest in new product areas such as final test and test management software. We use our close relationships with key customers to make product improvements that respond to such customers’ needs.

Engineering, research and development expenses were $16.2 million, $21.8 million and $31.6 million in 2004, 2003 and 2002, respectively, or 25.7%, 48.4% and 55.2% of net sales. Engineering, research and development expenses consist primarily of salaries, project materials, consultant fees, and other costs associated with our ongoing efforts in hardware and software product development and enhancement. It is expected that these expenses will decrease in absolute dollars and as a percentage of net sales in 2005 from 2004 levels.

Marketing, Sales and Service

We sell our products directly to end-users through a direct sales force and independent representatives. We generally sell product on net 30-day terms to most customers. Other, primarily foreign, customers are required to deliver a letter of credit typically payable upon product delivery. We generally warrant our products for a period of up to 12 months from shipment for material and labor repair. Installation and certain training are customarily included in the price of the product. Customers may enter into repair and maintenance service contracts covering our products. Our field engineers provide customers (with products not under warranty or service contracts) with call out repair and maintenance services for a fee. For a fee, we train customer employees to perform routine service.

We maintain sales and service offices in strategic locations throughout the United States. In Europe, we maintain sales and service offices in France, and in Asia, we maintain offices in the People’s Republic of China, Singapore and Taiwan.

Customers

We sell our products to leading semiconductor manufacturers and contract test companies throughout the world. In 2004, ST Microelectronics and Atmel each accounted for more than 10% of our net sales. International

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sales represented 63%, 65% and 48% of our net sales in 2004, 2003 and 2002, respectively. These sales represent the combined total of export sales made by United States operations and all sales made by foreign operations.

Manufacturing and Suppliers

Our assembly equipment manufacturing activities consist primarily of integrating components and subassemblies to create finished prober, spares and upgrades configured to customer specifications. We schedule production based upon firm customer commitments and anticipated orders during the planning cycle. In December 2002, we completed our move of equipment manufacturing from San Jose, California to Singapore to reduce production costs. In addition to rapid product innovation, our wafer prober market is subject to significant price competition and cost reduction is required. Certain of the components and subassemblies included in our products are obtained from a single source. However, we believe that alternative sources exist or can be developed.

Quality control is maintained through the assembly and test process, with documented instructions and test procedures and final inspection for all manufactured equipment prior to shipment. We train many of our employees in basic quality skills and regularly participate in quality sharing meetings with other equipment manufacturers and customer quality audits of procedures and personnel. We are ISO 9001/2000 and ISO 14001/1996 Certified.

Backlog

Our backlog was $8.3 million and $13.1 million as of December 31, 2004 and 2003, respectively. Our backlog consists of product orders for which a customer purchase order has been received and which is scheduled for shipment or is earned within the next twelve months. Orders are subject to cancellation or rescheduling by the customer, sometimes with a cancellation charge. Due to timing of order placement and product lead times, possible changes in product delivery schedules and cancellation of product orders and because our sales will often reflect orders shipped in the same quarter received, our backlog at any particular date is not necessarily indicative of actual sales for any succeeding period. Backlog also includes deferred revenue comprised of products shipped (but not recognizable as revenue per our revenue recognition policy), maintenance revenue that is being amortized over twenty-four months or less, and services earned or to be performed within the next year.

Competition

The semiconductor equipment industry is highly competitive. The principal competitive factors in the industry are product performance, reliability, price, service and technical support, product improvements, established relationships with customers and product familiarity. We believe that our products compete favorably with respect to each of these factors.

Our major competitors in the prober market and test floor management software segments are Tokyo Electron Limited and Tokyo Seimitsu, both of which are based in Japan. In these markets, these competitors have greater financial, engineering and manufacturing resources than we have, as well as larger service organizations and long-standing customer relationships. We cannot assure you that levels of competition in our particular product market will not intensify or that our technological advantages will be reduced or lost as a result of technological advances by competitors or changes in semiconductor processing technology. For a more detailed discussion of the competition we face, see “Factors that May Affect Results and Financial Condition.”

Patents, Trademarks, Copyrights and Other Intellectual Property

We believe that the success of our business depends more on the technical competence, creativity and marketing abilities of our employees, rather than on patents, trademarks and copyrights. Nevertheless, we have a policy of seeking patents when appropriate on inventions concerning new products and improvements as part of our ongoing research, development and manufacturing activities. We own various patents and have applied for additional patent protection in the United States and abroad for the technology in our products. We also have

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several registered United States and international trademarks. We maintain unregistered copyrights on our software and typically maintain the source code for our products as a trade secret.

We also rely upon trade secret protection for our confidential and proprietary information. We routinely enter into confidentiality agreements with our employees. There can be no assurance; however, that others will not independently gain information and techniques or otherwise gain access to our trade secrets or that we can meaningfully protect our trade secrets. For a more detailed discussion regarding risks related to our intellectual property, see “Factors that May Affect Results and Financial Condition.”

Employees

As of December 31, 2004, we employed 279 people. Many of our employees are highly skilled, and our success will depend in part upon our ability to attract and retain such employees, who are in great demand. We have never had a work stoppage or strike, and there are no employees represented by a labor union or covered by a collective bargaining agreement. We consider our employee relations to be good.

Item 2.    Properties

On December 16, 2004, we entered into an agreement with Integrated Design Technology (IDT) of Santa Clara, California, to sell our 260,000 square foot corporate headquarters facility located in San Jose, California and to lease back a portion of the property for a limited period of time with no rent payment. We are currently occupying 33% of the facility. See Note 14, Commitments and Contingencies.

In January 2002, we entered into a three-year operating lease for a 39,000 square foot manufacturing facility in Singapore with annual lease payments of approximately $0.4 million. This lease was renewed at the same rate in December 2004 for two additional years.

In February 2005, we entered into a five-year operating lease for a 78,000 square foot corporate headquarters facility in San Jose, California with annual lease payments ranging from nil to $1.0 million.

Item 3.    Legal Proceedings

We are not currently involved in any legal actions that we believe are material. From time to time, however, we may be subject to various claims and lawsuits by customers, suppliers, competitors, and employees arising in the normal course of business, including suits charging infringement or violations of antitrust laws. Such suits may seek substantial damages and, in certain instances, any damages awarded could be trebled.

Some customers using certain of our products have received letters from Technivison Corporation and the Lemelson Medical Education & Research Foundation, or Lemelson, alleging that the manufacture of semiconductor products infringes certain patents currently held by Lemelson. We believe that our products do not infringe the Lemelson patents and to the best of our knowledge, Lemelson has not asserted that we may be liable for infringing its patents. However, we have received notice from some of the customers receiving letters from Lemelson that, in the event it is determined that the customers’ actions infringe the Lemelson patents, the customers may seek reimbursement from us for some damages or expenses resulting from the infringement. We have in turn notified our suppliers that we may seek reimbursement from them for any resultant costs and fees we incur as a consequence of our customers being held liable for infringement of the Lemelson patents. In addition, some of our suppliers were notified that their equipment may infringe certain Lemelson patents. These suppliers are currently engaged in litigation with Lemelson as regards fourteen of Lemelson’s patents. In January 2004, the trial court held that the patent claims at issue were invalid, unenforceable and not infringed by the suppliers. Lemelson has appealed the decision. Given the pending appeal, and the inherent uncertain in litigation, we cannot assure you that the ultimate outcome will be favorable to us nor can we predict the effect of such litigation on our business.

Item 4.     Submission of Matters to a Vote of Security Holders

No matters were submitted to a vote of our security holders during the fourth quarter ended December 31, 2004.

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PART II

Item 5.    Market for the Registrant’s Common Equity and Related Stockholder Matters

Market Prices for Common Stock

Our common stock is traded on the Nasdaq National Market System under the symbol “EGLS.” The following table sets forth for the periods indicated the actual high and low sales prices per share of common stock as reported:

On March 8, 2005, the closing price of our common stock was $4.20.

We have never declared or paid cash dividends on the shares of common stock and we do not anticipate paying cash dividends in the foreseeable future. We currently intend to retain any future earnings to fund the development and growth of our business. As of March 8, 2005, we had approximately 6,241 stockholders of record.

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Item 6.    Selected Financial Data