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UNITED STATES

SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

FORM 10-K

For the year ended October 31, 2003

OR

Commission File Number 0-19807

SYNOPSYS, INC.

(Exact name of registrant as specified in its charter)

700 East Middlefield Road, Mountain View, California 94043

(Address of principal executive offices, including zip code)

(650) 584-5000

(Registrant’s telephone number, including area code)

Securities Registered Pursuant to Section 12(b) of the Act:    None

Securities Registered Pursuant to Section 12(g) of the Act:

Common Stock, $0.01 par value

(Title of Class)

Preferred Share Purchase Rights

(Title of Class)

Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.    x  Yes    ¨  No

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K.  ¨

Indicate by check mark whether the Registrant is an accelerated filer (as defined in Rule 12b-2 of the Act).     x  Yes    ¨  No

The aggregate market value of the voting and non-voting common equity held by non-affiliates computed by reference to the price at which the common equity was last sold as of the last business day of the Registrant’s most recently completed second fiscal quarter was $2,286,755,272. Excludes an aggregate of 94,085,796 shares of common stock held by officers and directors and by each person known by the Registrant to own 5% or more of the outstanding common stock on such date, giving effect to the two-for-one stock split completed on September 23, 2003. Exclusion of shares held by any of these persons should not be construed to indicate that such person possesses the power, direct or indirect, to direct or cause the direction of the management or policies of the Registrant, or that such person is controlled by or under common control with the Registrant.

On January 2, 2004, approximately 156,562,816 shares of the Registrant’s Common stock, $0.01 par value, were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

None.

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SYNOPSYS, INC.

ANNUAL REPORT ON FORM 10-K

Year ended October 31, 2003

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PART I

This Annual Report on Form 10-K, including Item 1, “Business,” includes forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934 that involve risks, uncertainties and assumptions. If these risks or uncertainties materialize, or if our assumptions are incorrect, our actual results could differ materially from those expressed or implied by these forward-looking statements. These statements include, but are not limited to statements concerning: our business, product and platform strategies; benefits we expect from previous and future acquisitions; completion of development of our unfinished products or further development or integration of our existing products; the shift of semiconductor manufacturing to 130 nanometer and below silicon processes; the expected customer benefits of the Milkyway^™ design database; our future research and development spending; continuation of current industry trends towards vendor consolidation; customer interest in more highly integrated tools and design flows; our expectations of the continuing success of our intellectual property and new ventures initiatives; and our expectations of our future liquidity requirements. For a discussion of certain risks or uncertainties which could cause our actual results to differ materially from those we project in these forward-looking statements, please see Part II, Item 7, “Factors That May Affect Future Results” under Management’s Discussion and Analysis of Financial Condition and Results of Operations below. The information we include in this Form 10-K is as of its filing date with the Securities and Exchange Commission and future events or circumstances could differ significantly from the forward-looking statements included in this report. We assume no obligation, and do not intend, to update these forward-looking statements.

Item 1. Business

Introduction

Synopsys, Inc. (Synopsys) is the world leader in electronic design automation (EDA) software used to design complex integrated circuits (ICs) and systems-on-chips (SoCs) in the global semiconductor and electronics industries. Our software and intellectual property products and design services provide a complete IC design and verification solution from original concept to the actual chip, enabling our customers to bring advanced products to market quickly.

We incorporated in 1986 in North Carolina and reincorporated in Delaware in 1987. Our headquarters are located at 700 East Middlefield Road, Mountain View, California 94043, telephone number (650) 584-5000. We have more than 60 offices throughout North America, Europe, Japan and Asia.

Our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, Proxy Statements relating to our annual meetings of stockholders, Current Reports on Form 8-K and amendments to these reports are available, free of charge, on our Internet website (www.synopsys.com). We post these reports as soon as practicable after we file them with the Securities and Exchange Commission.

The Role of EDA in the Electronics Industry

Continuing technology advances in the semiconductor industry have dramatically increased the feature density, speed, power efficiency and functional capacity of semiconductors (also referred to as integrated circuits, ICs or chips).

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Combined, these advances in semiconductor technology have driven development of lower cost, higher performance computers, wireless communications networks, cell phones, hand-held personal devices, Internet routers and a wealth of other electronic devices. Each advance, however, has introduced new challenges for all participants in semiconductor production, including designers, manufacturers, equipment manufacturers and EDA software suppliers.

The IC Design Process

EDA software is central to the IC design process, as it enables designers to:

In simplified form, IC design consists of system design, logic design, functional verification, physical design and physical verification.

System Design.    In system design, the designer describes the chip’s desired functions in very basic terms using a specialized high-level computer language, typically Verilog or VHDL. This phase yields a relatively high-level, “register transfer level” (RTL) description of the chip. System design is an early stage market segment for EDA companies, as most EDA products have focused to date on logic design, functional verification and physical design and verification.

Logic Design.    Logic design, or “synthesis,” programs convert the RTL code into a logical diagram of the chip, and produce a data file known as a “net list” describing the various groups of transistors, or “gates,” to be built on the chip. Related programs insert into the design the additional circuitry that will be needed to test the chip after manufacture.

In a growing number of designs, logic synthesis is performed together with a portion of physical design. This combined process, known as “physical synthesis,” produces a data file describing the chip plus a portion of the chip’s physical layout. Also, in a growing number of SoCs, designers are increasingly performing “design planning” in which the designer determines the location of the major functional “blocks” on the SoC prior to logic synthesis.

Functional Verification.    Before and after logic design, the designer uses testbench automation and other verification tools to simulate large sets of inputs that a given IC design might confront in real-life operation. By running these extensive tests, the designer can verify that the design will function as intended.

Physical Design.    In the physical design stage, the designer plans the physical location of all of the transistors and each of the wires connecting them with a “place and route” tool. The designer first determines the location on the chip die for each block of the chip, as well as the location for each transistor within each block, a process known as “placement.” Then the designer adds the connections between the transistors, a process known as “routing.” The output of place and route programs is one or more data files that can be read by physical verification programs (as described below) or by the equipment used to manufacture the chip.

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Physical Verification.    Before sending the chip design files to a manufacturer for fabrication, the designer must perform a series of further verification steps, confirming again that the chip will still operate at the desired speed and checking to make sure that the final design complies with the specific requirements of the fabrication facility that will manufacture the chip. The designer may need to add features to the design to ensure that the chip can be manufactured successfully. The completion of this final phase is called “tapeout.”

In actual chip design, each of these steps has a number of additional elements, and designers often undertake the various design and verification steps in a different order than described above, and repeat one or more steps multiple times. Further, several of the steps, especially logic design and physical design, are becoming more integrated with each other. If at any stage of the process the designer determines the chip design will not perform as intended, the designer must go back one or more steps and correct the problem, then continue through subsequent steps. Recreating a chip’s logic design, devising and performing simulation over again, and other iterations all take time. Each such iteration adds significant costs, and makes it more difficult for the designer to meet time-to-market goals.

Current Issues Facing IC Designers

As chip technology continues to advance, our customers face three principal types of interrelated challenges:

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Synopsys Overview

We provide products and services that help our customers meet the challenges of designing leading-edge ICs. As a result of our mid-2002 acquisition of Avant! Corporation (Avant!), we now offer a comprehensive suite of system design, logic design, functional verification, physical design and physical verification products. Our March 2003 acquisition of Numerical Technologies, Inc. (Numerical) expanded our offerings of manufacturing technologies and products geared towards small geometry designs. We also sell the broadest array of pre-verified intellectual property (IP) components of any company in the EDA industry. Finally, we offer a full range of professional services, including turnkey design services, design assistance and methodology consulting.

We market our products worldwide and offer comprehensive customer service, education, consulting and support as integral components of our product offerings. We market our products primarily through our direct sales force. We have licensed our products to most of the world’s leading semiconductor, computer, communications, electronics and device companies.

Strategy

Our strategy has three principal components. First, we have historically focused, and will continue to focus, on providing our customers the most technologically advanced products to address each step in the IC design process. Second, building on the strength of our individual products, we will continue to focus on developing broad, increasingly integrated “platforms,” or collections of key individual products that are tightly integrated through the use of common technologies, to deliver enhanced value. In fiscal 2003, we created two distinct platforms: our Galaxy Design Platform and our Discovery Verification Platform. Third, we will expand our product offerings in areas offering the potential for rapid growth. For example, we have undertaken initiatives in both the intellectual property and design for manufacturing segments as described below under Products and Services.

Organization

We operate in a single segment and are currently organized into four primary groups: Implementation, Verification, Solutions and New Ventures.

Our other groups include Worldwide Sales, Worldwide Application Services, Finance, Human Resources and Facilities, and Chief Technology Office.

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Products and Services

Our products and services focus on the principal needs of semiconductor designers and, at a business level, are divided into the four groups specified above. We provide financial information regarding our products and services under Part II, Item 7, Management’s Discussion and Analysis of Financial Condition and Results of Operations—Results of Operations—Revenue—Product Groups.

Implementation Group

Galaxy Design Platform.    In February 2003, we announced the combination of many of our leading IC design products into a single, unified platform called the Galaxy^™ Design Platform. Galaxy includes the following products:

With the Galaxy Design Platform, our goal is to provide our customers a single, integrated IC design platform based on leading individual products which incorporates common libraries and consistent timing, delay calculation and constraints throughout the design process using our open Milkyway database, and yet allows designers the flexibility to integrate internally developed and third-party tools. With this advanced functionality,

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common foundation and flexibility, our Galaxy Design Platform should help reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC designs.

Verification Group

Discovery Verification Platform.    Also during fiscal 2003, we introduced our Discovery^™ Verification Platform. The Discovery Platform combines many of our verification and nanometer level analysis tools in a unified environment to provide high performance and efficient interaction among these technologies. The Discovery Verification Platform includes the following products:

The Discovery Verification Platform also includes our Discovery AMS platform, a subset of the above technologies tuned to perform verification on analog and mixed analog-and-digital designs, and supports the latest Accellera SystemVerilog language standard, Verilog, VHDL, mixed-HDL, SystemC, and for analog mixed-signal based methodologies, Verilog-AMS and SPICE.

The increasing size and complexity of today’s ICs and SoCs have vastly increased the time and effort required to verify chip designs, with test creation and verification now consuming up to 70% of the total design time for a given IC. Our Discovery Platform combines our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to significantly improve the speed, breadth and accuracy of our customers’ verification efforts on complex chip designs, increasing their productivity and helping them deliver their products to market faster.

Solutions

    Synopsys’ Solutions Group includes our portfolio of IP products and components and our Consulting Services Group.

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Intellectual Property Products.    As IC designs continue to grow in size, reusing proven design blocks is an increasingly important way to reduce overall design cost and cycle time. Enabling reuse of IP requires a significant methodology shift from traditional IC design. In the past, designs were intimately tied to a particular semiconductor process technology or design methodology, making reuse of design blocks from one chip design to the next both difficult and costly. More recently, IC companies have been able to increasingly reuse pre-designed and verified IP components, particularly those that implement basic or standardized functions. The ability to reuse such IP allows IC companies to focus their design teams on designing the chip features that will give its products a competitive advantage. Using pre-designed IP can also reduce a chip designer’s verification risk by ensuring that the “designed in” portions of the chip are “pre-verified” and thus high quality. Because of the increasing importance of pre-designed IP, and in order to minimize the risk and effort in acquiring IP from a myriad of smaller suppliers, IC designers are beginning to consolidate their IP purchases from fewer vendors who can provide a reliable, comprehensive portfolio of proven IP.

Our IP products include:

Finally, Synopsys’ Star IP program permits DesignWare library users to gain access to popular microprocessor cores from leading semiconductor and IP companies. We have worked with these companies to improve the reusability of these microprocessor cores as well as to integrate them with other DesignWare microprocessor subsystems. The program includes cores from companies like MIPS, NEC and Infineon, and in 2003 we added a PowerPC microprocessor from IBM.

Professional Services.  We provide a comprehensive portfolio of consulting services covering all critical phases of the SoC development process, as well as systems development in wireless and broadband applications. We offer customers a variety of engagement models ranging from project assistance, which helps our customers design, verify and/or test their chips and improve their design processes, to full turnkey development.

New Ventures

Our New Ventures Group includes a number of products and initiatives relating to analog/mixed signal IC design and verification and design for manufacturing.

Analog Mixed-Signal Tools.  Our Cosmos^™ tool is used to create analog designs. Cosmos uses schematic-driven layout to place and route full-custom ICs. The New Ventures Group also manages development and marketing of our NanoSim and HSPICE tools described above under Discovery Verification Platform.

Design for Manufacturing.  With the acquisitions of Avant! and Numerical, we offer a variety of products and technologies used at the intersection of IC design and manufacturing which address a variety of issues, principally those encountered using photolithography techniques to manufacture ICs when advanced ICs have feature dimensions smaller than the wavelength of light used to expose those dimensions during production. We address these markets through our Design for Manufacturing initiatives, which include:

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Customer Service and Technical Support

We believe a high level of customer service and support is critical to the adoption and successful use of our products. We provide technical support for our products through both field- and corporate-based application engineering groups. Customers who purchase Technology Subscription Licenses (TSLs) receive software maintenance services, also known as “post contract support” (PCS), bundled with their license fee. Customers who purchase term licenses and perpetual licenses may purchase these services separately. See Product Sales and Licensing Agreements below.

Software maintenance services include minor product enhancements we develop, bug fixes and access to our technical support center for primary support. Software maintenance also includes access via electronic mail and the World Wide Web to SolvNet®, our web-based support solution that lets customers quickly seek answers to design questions or more insight into design problems. SolvNet gives customers access to Synopsys’ complete design knowledge database using sophisticated information retrieval technology. Updated daily, it includes documentation, design tips, and answers to user questions. Customers can also engage our application consultants, our worldwide network of product experts, for additional support needs.

Customer Education Services

We offer training workshops designed to increase customer design productivity while using our products. Workshops cover Synopsys tools and methodology used in our design and verification tool flows, as well as specialized modules addressing system design, logic design, physical design, simulation and test. We offer regularly scheduled workshops in Mountain View, California; Austin, Texas; Marlboro, Massachusetts; Reading, England; Rungis, France; Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other locations. We also schedule on-site workshops worldwide at our customers’ facilities or other locations. Approximately 8,500 engineers attended Synopsys workshops during fiscal 2003.

Product Warranties

We generally warrant our products to be free from defects in media and to substantially conform to material specifications for a period of 90 days. We also typically provide our customers limited indemnities with respect to claims that their use of our design and verification software products infringe on United States patents, copyrights, trademarks or trade secrets. We have not experienced material warranty or indemnity claims to date.

Support for Industry Standards

We actively create and support standards we believe will help our customers increase productivity, improve interoperability of tools from different vendors, and solve design problems. Standards in the EDA industry can be established by formal accredited committees, by licensing made available to all, or through open source licensing.

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Synopsys’ products support many formal standards, including the most commonly used hardware description languages, VHDL, Verilog HDL, SystemVerilog and SystemC, as well as numerous industry standard data formats for the exchange of data between our tools, other EDA vendor’s products and applications customers develop internally.

Synopsys is a board member and/or participant in the following major EDA standards organizations: Accellera, a not-for-profit formal standards organization that drives language-based standards for systems, semiconductor, and design tool companies; the interoperability committee of the EDA Consortium, which helps promote quality and interoperability among EDA products from different vendors; the Institute of Electrical and Electronics Engineers (IEEE), a non-profit, technical professional association and a leading developer of global industry standards; the Virtual Socket Interface Alliance (VSIA), an industry group formed to promote standards that facilitate the integration and reuse of functional blocks of intellectual property; and the Open SystemC Initiative (OSCI), a non-profit organization that manages SystemC, a language developed by Synopsys and donated to OSCI, with representation from the systems, semiconductor, IP, embedded software and EDA industries.

Synopsys’ TAP-in program provides interface standards to all companies through an open source licensing model. Synopsys manages changes and enhancements that come from the community of licensees. Synopsys, other EDA companies and EDA customers use these standards to facilitate interoperability of their tools. The standards offered through TAP-in include Liberty for library modeling, SDC for design constraints, SAIF for switching activity and OpenVera for hardware verification. Synopsys’ common database, Milkyway, is available for tool integration by EDA vendors through our MAP-in program.

Synopsys’ products are written mainly in the C and C++ languages and utilize industry standards for graphical user interfaces. Our software runs under UNIX operating systems, such as Solaris and HP-UX, and under the RedHat Linux operating system. Synopsys’ products are offered on the most widely used hardware platforms, including those from Sun Microsystems, Hewlett-Packard, IBM and PCs that are based upon Intel and AMD microprocessors.

Sales, Distribution and Backlog

We market our products and services primarily through direct sales and application engineers or support personnel in the United States and principal foreign markets. We employ highly skilled engineers and technically proficient sales persons in order to understand our customers’ needs and explain and demonstrate the value of our products.

In fiscal 2003, 2002 and 2001, foreign revenues represented 43%, 35% and 37%, respectively, of Synopsys’ total revenue. Additional information relating to domestic and foreign operations is contained in Note 9 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data. Information relating to risks associated with foreign operations are described in Part II, Item 7, Management’s Discussion and Analysis of Financial Condition and Results of Operations—Factors That May Affect Future Results—Stagnation of foreign economies, foreign exchange rate fluctuations or other international issues could adversely affect our performance.

We have sales/support centers throughout the United States, in addition to our Mountain View, California headquarters. Outside the United States, we have sales/support offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People’s Republic of China, Singapore, South Korea, Sweden, Switzerland, Taiwan and the United Kingdom. Our foreign headquarters is in Dublin, Ireland. Our offices are further described under Part I, Item 2, Properties.

In limited circumstances, we use distributors to assist us in the sale of certain products in specified markets. See Note 11 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data for additional information about one of our distributors.

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Historically, orders and revenue have been lowest in our first fiscal quarter and highest in our fourth fiscal quarter, with a material decline between the fourth quarter of one fiscal year and the first quarter of the next fiscal year. We expect the first fiscal quarter will remain our lowest orders and revenue quarter; orders and revenue in other quarters will vary based on the particular timing and type of individual contracts entered into with large customers.

Synopsys’ aggregate non-cancelable backlog was approximately $1.6 billion on November 1, 2003, representing a 17% increase from the end of the prior fiscal year. Aggregate non-cancelable backlog includes deferred revenue, operational backlog and financial backlog and excludes all items relating to consulting services. Deferred revenue represents orders for software products, license maintenance and other services which have been delivered and billed to the customer but the revenue has not yet been earned. Operational backlog consists of orders for system and software products sold under perpetual or term licenses and TSLs with customer requested ship dates within three months which have not been shipped. Financial backlog consists of future installments to be billed and received from the customer not yet currently due and payable. In the case of a TSL, financial backlog includes the full amount of the committed non-cancelable order, less any amount of revenue that has been recognized on such TSL.

We have not historically experienced significant order cancellations.

Research and Development

Our future performance depends in large part on our ability to further integrate our design and verification platforms, maintain and enhance our current products, develop new products, and meet an expanding range of customer requirements. Research and development on existing and new products is primarily conducted within each business unit. Synopsys also maintains an Advanced Technology Group, which is responsible for exploring new technologies and maintaining strong research relationships outside Synopsys within both industry and academia.

During fiscal 2003, 2002 and 2001, research and development expenses, net of capitalized software development costs, were $285.9 million, $225.5 million and $189.8 million, respectively. Synopsys capitalized software development costs were approximately $2.6 million, $1.6 million and $1.0 million in fiscal 2003, 2002 and 2001, respectively. We anticipate that we will continue to commit substantial resources to research and development in the future.

Manufacturing

Synopsys’ manufacturing operations consist of packaging and shipping CD-ROMs containing software products and the related documentation. We currently conduct these activities through contract vendors, who provide the majority of CD-ROM replication and on-demand printing and distribution of product media and documentation. We deliver an increasing proportion of our software products by electronic means rather than by shipping disks. When specified by the customer or required by law, Synopsys delivers disks to the customer’s site. We typically deliver our software products within 10 days of acceptance of customer purchase orders and execution of software license agreements unless the customer requests otherwise.

Competition

The EDA industry is highly competitive. We compete against other EDA vendors and against our customers’ own design tools and internal design capabilities. In general, we compete on product quality and features, post-sale support, interoperability with other vendors’ products, price, payment terms and, as discussed below, the ability to offer a complete design flow.

Our competitors include companies that offer a broad range of products and services, such as Cadence Design Systems, Inc. (Cadence) and Mentor Graphics Corporation, and companies that offer products focused on

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a discrete phase or phases of the integrated circuit design process. During the recent semiconductor downturn, we have increasingly competed on the basis of payment terms and price. During fiscal 2003, we increasingly agreed to extended payment terms on our TSLs, negatively affecting our deferred revenue and cash flow from operations. In addition, in certain situations our competitors offer aggressive discounts on their products. As a result, average prices may fall, and we may lose potential business where we believe a given discount is not in our best interests.

Increasingly, EDA companies compete on the basis of design flows involving integrated logic and physical design products rather than on the basis of individual point tools performing a discrete phase of the design process. The need to offer an integrated design flow will become increasingly important as ICs grow more complex. While we have introduced design and verification platforms that integrate many of the products required to design an IC into a unified flow, we face significant competition from companies that also offer their own integrated design flows, such as Cadence and Magma Design Automation, Inc. To be successful in the future, we believe we must further integrate our design and verification products, which will continue to require significant engineering and development work. There can be no guarantee that we will be able to offer a competitive complete design flow to customers. If customers fail to adopt our design and verification platforms or if we are unable to develop new discrete design tools or enhance existing ones to add increased functionality or performance, our financial condition and results of operations will be materially and adversely affected.

Product Sales and Licensing Agreements

We typically license our software to customers under non-exclusive license agreements that transfer title to the media only and restrict use to specified purposes within specified geographical areas. The majority of our licenses are network licenses that allow a number of individual users to access the software on a defined network. License fees depend on the type of license, product mix and number of copies of each product licensed. In certain cases, customers have the right to use our products over a wide-area network or to exchange a portion of the software under license for different software products of equal value.

We currently offer our software products under three license types: renewable TSLs, renewable term licenses, and perpetual licenses. For a full discussion of these licenses, see Part II, Item 7, Management’s Discussion and Analysis of Financial Condition and Results of Operations—Critical Accounting Policies—Revenue Recognition below.

With respect to our DesignWare Core intellectual property products, we typically license those products to our customers under nonexclusive license agreements which provide usage rights for specific applications. Fees under these licenses are typically charged on a per design basis plus, in some cases, royalties.

Finally, our professional services teams typically operate under consulting agreements with our customers with statements of work specific to each project.

Proprietary Rights

Synopsys primarily relies upon a combination of copyright, patent, trademark and trade secret laws and license and nondisclosure agreements to establish and protect its proprietary rights. Our source code is protected both as a trade secret and as an unpublished copyrighted work. However, third parties may develop similar technology independently. In addition, effective copyright and trade secret protection may be unavailable or limited in certain foreign countries. We currently hold United States and foreign patents on some of the technologies included in our products and will continue to pursue additional patents in the future.

Under our customer agreements and other license agreements, in many cases we offer to indemnify our customer if the licensed products infringe on a third party’s intellectual property rights. As a result, we are from time to time subject to claims that our products infringe on these third party rights. For example, we are currently

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defending some of our customers against claims that their use of one of our products infringes a patent held by a Japanese electronics company. We believe this claim is without merit and will continue to vigorously pursue this defense.

These types of claims can result in costly and time-consuming litigation, require us to enter into royalty arrangements, subject us to damages or injunctions restricting our sale of products, require us to refund license fees to our customers or to forgo future payments or require us to redesign certain of our products, any one of which could materially and adversely affect our business.

Employees

As of November 1, 2003, Synopsys had 4,362 employees, of whom 2,885 were based in North America and 1,477 were based outside of North America. Our future financial results depend in part upon the continued service of our key technical and senior management personnel and our continuing ability to attract and retain highly qualified technical and managerial personnel. We participate in a dynamic industry, with start-up activity, and our headquarters is in Silicon Valley, where competition for the most highly skilled technical, sales and management employees is intense. Experience at Synopsys is highly valued in the EDA and general electronics industry, and our employees are recruited aggressively by our competitors and by start-up companies in many industries. We have periodically experienced significant employee turnover. We can provide no assurances that we can retain our key managerial and technical employees or continue to attract or retain additional highly qualified technical and managerial personnel in the future. None of our employees is represented by a labor union. We have experienced no work stoppages, and we believe our employee relations are good.

Item 2. Properties

Synopsys’ principal offices are located in four adjacent buildings in Mountain View, California, which together provide approximately 400,000 square feet of available space. This space is leased through February 2015. Within one half mile of these buildings, in Sunnyvale, California, Synopsys occupies approximately 200,000 square feet of space in two adjacent buildings, which are under lease through April 2007, and approximately 72,000 square feet of space in a third building, which is under lease through April 2007. We use these buildings for administrative, marketing, research and development and support activities. In addition, Synopsys leases 16,000 square feet of space in Pleasanton and Fremont, California as telecommute centers. As a result of fiscal 2002 and 2003 acquisitions, we assumed leases of approximately 55,000 square feet of space in San Jose, California, 7,500 square feet of space in Pleasanton and 5,000 square feet of space in Austin, Texas, none of which we currently occupy.

Synopsys owns two buildings totaling approximately 230,000 square feet on approximately 43 acres of land in Hillsboro, Oregon, which we use for administrative, marketing, research and development and support activities. In addition, we lease approximately 80,000 square feet of space in Marlboro, Massachusetts for sales and support, research and development and customer education activities. This facility is leased through January 2009.

Synopsys owns a fourth building in Sunnyvale, California with approximately 120,000 square feet, which is leased to a third party through February 2009. Synopsys also owns 34 acres of undeveloped land in San Jose, California and 13 acres of undeveloped land in Marlboro, Massachusetts.

Synopsys currently leases 32 other offices throughout the United States primarily for sales and support.

Synopsys leases approximately 45,000 square feet in Dublin, Ireland for its foreign headquarters and for research and development purposes. This space is leased through April 2026. In addition, Synopsys leases 34 foreign sales and service offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People’s Republic of China, Singapore, South Korea, Sweden, Switzerland, Taiwan

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and the United Kingdom. We also lease research and development facilities in Canada, France, Germany, India, Ireland, Japan, Korea, the Netherlands, the People’s Republic of China, South Korea, Sweden, Taiwan and the United Kingdom.

We believe our properties are adequately maintained and suitable for their intended use and that our facilities have adequate capacity for our current needs.

Item 3. Legal Proceedings

Synopsys is currently a party to various claims and legal proceedings which arise in the ordinary course of business. If management believes a loss arising from these actions is probable and can reasonably be estimated, we record the amount of the loss or the minimum estimated liability when the loss is estimated using a range and no point within the range is more probable than another. As additional information becomes available, we assess any potential liability related to these actions and revise our estimates, if necessary. Based on currently available information, management believes the ultimate outcome of these actions, individually and in the aggregate, will not have a material adverse effect on our financial position or overall trends in results of operations. However, litigation is inherently uncertain, and we could therefore receive unfavorable rulings. An unfavorable ruling could include monetary damages or an injunction prohibiting Synopsys from selling one or more products. An unexpected unfavorable ruling could have a material adverse impact on our results of operations for the period in which the ruling occurs or future periods.

Item 4. Submission of Matters to a Vote of Security Holders

No matters were submitted for a vote of security holders during the fourth quarter of fiscal 2003.

Executive Officers of the Registrant

The executive officers of Synopsys and their ages as of December 31, 2003, are: