SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

 

 

FORM 10-K

 

 

 

 

 

Indicate by check mark whether the registrant: (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.  Yes  ý    No  o

 

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K.  ý

 

Indicate by check mark whether the registrant is an accelerated filer (as defined in Rule 12b-2 under the Securities Exchange Act of 1934) Yes  o    No  ý

 

As of September 30, 2002, the issuer had outstanding 30,784,296 shares of common stock.  The aggregate market value of the shares of the registrant’s common stock, $0.001 par value per share, held by non-affiliates of the registrant (all stockholders other than officers, directors and 5% or greater stockholders) as of that date was $793,721(based upon an average of the closing bid and asked price of $0.05 per share as of such date, as reported the over-the-counter “pink sheets” published by Pink Sheets LLC).

 

As of March 31, 2003, the registrant had outstanding 30,809,667 shares of common stock.

 

 

TABLE OF CONTENTS

 

PART I
Item 1	Business
Item 2	Properties
Item 3	Legal Proceedings
Item 4	Submission of Matters to a Vote of Security Holders
PART II
Item 5	Market for Registrant’s Common Stock and Related Stockholder Matters
Item 6	Selected Financial Data
Item 7	Management’s Discussion and Analysis of Financial Condition and Results of Operations
Item 7A	Quantitative and Qualitative Disclosures about Market Risk
Item 8	Financial Statements and Supplementary Data
Item 9	Changes in and Disagreements with Accountants on Accounting and Financial Disclosure
PART III
Item 10	Directors and Executive Officers of the Registrant
Item 11	Executive Compensation
Item 12	Security Ownership of Certain Beneficial Owners and Management and Related Stockholder Matters
Item 13	Certain Relationships and Related Transactions
Item 14	Controls and Procedures
Item 15	Principal Accountant Fees and Services
PART IV
Item 16	Exhibits, Financial Statement Schedules, and Reports on Form 8-K

 

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PART I

 

GENERAL

 

FORWARD-LOOKING STATEMENTS

 

This report contains forward-looking statements that involve substantial risks and uncertainties.  In some cases you can identify these statements by forward-looking words such as “anticipate,” “believe,” “could,” “estimate,” “expect,” “intend,” “may,” “should,” “will,” and “would” or similar words.  You should read statements that contain these words carefully because they may discuss our future expectations, contain projections of our future results of operations or of our financial position or state other “forward-looking” information.  However, there may be events in the future that we are not able to accurately predict or control.  The factors listed in Item 7 under the caption “Risk Factors,” as well as any cautionary language in this report, provide examples of risks, uncertainties and events that may cause our actual results to differ materially from the expectations we describe in our forward-looking statements.  You should be aware that the occurrence of any of the events described in these risk factors and elsewhere in this report could have a material adverse effect on our business, financial condition and results of operations.

 

ITEM 1.  BUSINESS

 

OVERVIEW

 

We provide yield optimization solutions for manufacturers of semiconductors and flat panel displays.  We offer scalable yield optimization solutions that permit companies to accelerate the process by which they develop technology as well as identify, measure, and correct sources of failure in the production process.  Our customizable software products and proprietary TestChip Technology Development Intellectual Property (“TestChip IP”)  enable our customers to quickly identify and correct yield-limiting factors in their design, technology development and manufacturing processes.  Our integrated tools analyze parametric, bin/sort, bitmap, MES, defect and design layout data, as well as monitor the changes made to process “recipes.”  This analysis and monitoring results in faster improvements in yield or “yield learning.”

 

We have principally conducted business as Heuristic Physics Laboratories, Inc. (“HPLI”), a California corporation, since 1989.  HPLI merged on July 30, 2001 with a wholly-owned subsidiary of HPL Technologies, Inc., a newly organized Delaware corporation (sometimes referred to in this report as “HPL”, the “Company”, “we”, “our” or “us”), and each outstanding share of HPLI common stock was converted into 1.7 shares of HPL common stock.  As a result of the merger, HPLI effectively reincorporated into Delaware and we adopted a holding company structure.  Unless we specify otherwise, all references to the Company and HPL in this report refer to HPL and its subsidiaries.  Our principal executive offices are located at 2033 Gateway Place, Suite 400, San Jose, California 95110 and our telephone number is (408) 437-1466.

 

In July 2002, our Audit Committee initiated an investigation into financial and accounting irregularities involving revenue reported during prior periods. Based on the investigation, we discovered that a material amount of revenue was improperly recognized during 2001 and 2002, primarily in connection with fictitious sales to an international distributor. Accordingly, we restated our previously issued financial statements as of and for the years ended March 31, 2002 and 2001. During the investigation, Y. David Lepejian, the Company’s former President and Chief Executive Officer, was removed from all positions with the Company. In addition, the Vice President of Administration and the Chief Financial Officer of the Company were replaced.  None of these former officers participated in the preparation or oversight of the restatement of our financial statements or any other financial information or reports since the date of their respective departures.  Subsequent to his termination, Mr. Lepejian entered into a consent decree with the SEC and has pleaded guilty to one count of wire fraud.  The Company is a party to numerous lawsuits relating to these events.  See, Item 3 — Legal Proceedings.

 

INDUSTRY BACKGROUND

 

The semiconductor product development process can be grouped into three broad stages: 1) process technology development, 2) design, and 3) manufacturing.  These stages are described below:

 

1)                                      Process Technology Development.  Semiconductor production begins with the development of “process technology,” during which a semiconductor fabricator determines device characteristics and assess the yield impact of manufacturing margins.  Based on the results of the assessment, “design rules” are created to assure that products can be reliably produced in a given fabrication facility.  These design rules guide the product design process in the second stage of

 

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product development, described below.

 

2)                                      Design.  The second stage of semiconductor production is product design.  Design involves using complex software to place and connect individual electrical components (transistors) to construct the functionality of a product.  A leading-edge design can call for millions of transistors and interconnections on a square centimeter of silicon.  For a semiconductor product to be manufactured and work properly, it must be designed with exact precision and expressly for a given semiconductor process technology, described above.

 

3)                                      Manufacturing.  The third step in the semiconductor development process is manufacturing.  Manufacturing requires hundreds of individual processing steps to form patterned layers of material on a wafer to create transistors and connect them to form the desired electronic circuitry or function.  Additionally, the manufacturing process includes packaging and testing of the individual chips themselves.  In the case of new technology, interaction between the various wafer fabrication processes and/or the design frequently cause new types of defects and new sources of failure.  Constant and accurate measurement and inspection are required to find defects and eliminate defect sources during wafer manufacturing as well as assembly and test processes.  The early detection and subsequent resolution of yield problems can result in significant cost savings to the manufacturer.

 

Importance of Yield

 

Yield is a measurement of the efficiency of a product development process.  Specifically, yield is the percentage of properly functioning devices produced at each stage in the manufacturing process.  Improvement of yield or “yield learning” is often challenging and involves the continual identification and resolution of the root causes of failure in the design and manufacturing process.    New products built with newer, less mature semiconductor manufacturing processes often start with very low yields because fabrication procedures and device technologies are not yet fully optimized.  During the transition from early fabrication to volume production, yield improvements are often difficult as production equipment and processes are stressed to maximize throughput.  Even as production volumes increase, yield often falls as new production equipment is brought on-line and test programs are enhanced to reduce test escapes.

 

Yield improvement is a multi-faceted challenge as thousands of factors in the semiconductor production process may affect yield.  These factors contribute to yield loss based on the sensitivity and margin of the design and manufacturing.  By definition, failures are random or systematic in nature.  Random failures are typically caused by arbitrary particles introduced into the fabrication process causing circuit faults such as a bridge between two adjacent metal lines.  Systematic failures emanate from non-random sources such as equipment or environmental changes, and design sensitivity or material property variations.  Due to yield learning, each successive generation of semiconductors become somewhat less sensitive to existing failure modes but remain susceptible to new failure modes.  This creates a need to capture and analyze more data to improve yields.  The sheer volume of data and the amount of complex analysis required has become an impediment to improving the yield learning curve.  To identify factors that affect yield in a new process, semiconductor companies must collect and analyze an immense (and growing) amount of data that is generated throughout the semiconductor product development lifecycle, often from several worldwide locations and, increasingly, from supply chain partners.  In any semiconductor fabrication facility, there are likely to be as many as 50 different sets and formats of data produced, each with thousands of individual parameters that need to be tracked.  While this data provides important clues to yield enhancement, the efficient collection, correlation and analysis across the various data sets presents a substantial challenge for the semiconductor industry.

 

High yield is an essential requirement for a profitable semiconductor business, especially during the introduction of new products.  Selling prices and profit margins are typically higher in the early stages of a new semiconductor product lifecycle.  A small acceleration along the yield learning curve can create disproportionately greater revenue and profitability.  Another benefit of fast yield ramp is the increased revenue that is associated with the measured speed of microprocessors, application specific integrated circuits (“ASICs”) and telecom devices.  High parametric yield enables parts to operate at higher frequencies and subsequently command higher selling prices.  As the product lifecycles advance, high yield can accelerate cost reductions and maximize efficiency gains.  These factors make it essential that semiconductor companies monitor and maintain yield on an ongoing basis throughout the entire product lifecycle.  In today’s volatile markets where capacity utilization rates fluctuate, yield improvement remains fundamental to business success.  Given the immense costs of a semiconductor fabrication facility and the economics of production efficiency, the rate of yield learning is a critical component in the profitability of a given semiconductor company.

 

Flat Panel Industry

 

The flat panel display (“FPD”) industry is entering the product phase where the price points for liquid crystal display televisions (“LCD-TVs”) and liquid crystal display-computer monitors make them preferable to cathode ray tube (“CRT”) technology.  The latest estimates predict the global FPD market will grow 143% to $65.1 billion by 2006.  The projected demand for LCD-TVs, forecast to be 76.5% compound annual growth rate, is expected to drive the majority of the FPD market.  Manufacturing cost

 

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reductions and new processes that shorten cycle time and improve performance are expected to accelerate demand from the manufacturing side.

 

The current move to new FPD substrate sizes (i.e. generations 5, 6 and 7) are expected to reduce manufacturing costs.  Additionally, new materials such as low-temperature poly-silicon are expected to improve product performance.  However, these changes present significant manufacturing and yield challenges.  As in the semiconductor industry, FPD yield optimization solutions help users quickly solve these problems by aggregating all yield-relevant data and providing high-powered analysis techniques to FPD engineers.  Using these systems, engineers spend less time gathering and preparing data and more time correcting yield problems.

 

Currently, most FPD yield enhancement tools are internally developed.  However, software development is not a core competency of the LCD manufacturer so their internal solutions tend to lack scalability and application integration.  HPL’s commercial FPD software yield solutions leverage our experience in the semiconductor industry.  HPL provides FPD engineers with fully integrated packages that encapsulate the collective best practices of the semiconductor industry.  In addition, HPL’s visualization and analysis modules meet the specific requirements of the display industry so that FPD manufacturers benefit from the full power and flexibility of the HPL Enterprise Yield Optimization Platform.

 

HPL PRODUCTS AND TECHNOLOGY

 

HPL provides an integrated suite of yield enhancement software solutions that enables customers to optimize yields in all three stages of semiconductor development:  process technology development, design and manufacturing.  Derived from years of experience working with leading semiconductor manufacturing companies, HPL has embedded much of the industry’s best practices directly into our yield optimization products.  HPL’s yield optimization software delivers high-impact business results by reducing the time to high yield through enhanced collaboration among process technology development, design and manufacturing, and streamlined data analysis.

 

YIELDirector™- Workflows

 

YIELDirector Workflows provide a development environment for rapid implementation of both interactive applications and/or sophisticated reporting for virtually any data from a wafer fabrication, packaging, or test step of the manufacturing process.  Applications are developed using a development environment where application development is 3 to 15 times faster than traditional techniques.  This allows customers to react to yield problems and deploy solutions very rapidly.  YIELDirector-Workflow can be used with HPL, customer developed, and third party systems.

 

YIELDirector-FPD

 

YIELDirector-FPD is a yield optimization solution built specifically for the flat panel display manufacturers.  YIELDirector-FPD leverages the best-in-class and highly scalable YIELDirector platform.  This enables FPD customers to integrate relevant manufacturing data into a seamless and powerful yield optimization environment.  YIELDirector-FPD is a premier commercial yield optimization solution targeted at the unique challenges of FPD manufacturing.

 

Recipe Management and Editing (“RME”)

 

RME is a universal enterprise solution that facilitates the management and control of process recipes directly from a central repository.  Process recipes are used to control the program process and metrology tools at every step in a semiconductor manufacturing process.  RME manages all production recipes from a single environment, which dramatically reduces product scrap, improves yield and increases productivity of semiconductor fabs.  A patented off-line editing module allows engineers to edit process recipes at their desk or anywhere on the corporate intranet without sacrificing security or increasing tool downtime.

 

Memory YIELDirector

 

Memory YIELDirector accelerates yield learning and problem resolution for DRAM, SRAM and Flash memory arrays on semiconductor devices.  Memory YIELDirector automates analysis of fab and test data for all memory types including embedded memory.  Using powerful analysis algorithms, Memory YIELDirector automatically descrambles and classifies failing bitmaps into unique signatures, and correlates them to in-line defect inspection data to determine the defect kill ratios.  Memory YIELDirector has powerful visualization algorithms that help correlate bitmap failures with fatal defects (defects that will cause a failure in the device) to enable rapid isolation of the root cause failures in memories.

 

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Odyssey™ Defect

 

Odyssey Defect is a production-proven defect data management solution that is in use at over seventy manufacturing sites worldwide.  Odyssey Defect delivers results efficiently and reliably, leveraging error-correcting processes to assure users of maximum up-time.  It has an open and equipment vendor-neutral architecture that supports most inspection, review and classification tools with a full range of charting, wafer mapping and statistic analysis.  Odyssey Defect is easy to use and provides high productivity with its all-in-one graphical user interface (“GUI”).  Odyssey Defect simplifies and automates in-line defect analysis to reduce cycle times, enabling engineers to address other critical yield-limiting issues.

 

Odyssey™ YMS

 

Odyssey YMS is a fab-wide data management tool for improving yields and productivity by efficiently correlating different data types to quickly deduce the root cause of manufacturing problems.  Advanced Data Mining algorithms uncover hidden correlations and easy-to-use templates automate daily and repetitive analyses at preset intervals.  Odyssey YMS includes Odyssey Defect and several additional powerful analysis modules including:

 

Metrology, which collects and analyzes data from inline production equipment, such as resistivity, critical dimension, wafer flatness, and oxide and etch rate monitors;

 

Parametric, which analyzes data collected from inline Wafer Electrical Test and end of line Wafer Acceptance Test automatic test equipment.  Standard support is included for systems such as Agilent and Keithley testers;

 

BIN, which utilizes final wafer sort (chip probe) data, collected with Automated Test Equipment from companies such as Teradyne, Advantest, Credence, LTX and Agilent;

 

BIT, which analyzes failing bit signatures, failing patterns per die and per wafer and graphically overlays failure data with defect data; and

 

WIP, which encompasses process flow, tool, and route information collected by Manufacturing Execution Systems, such as PROMIS™, FACTORYworks™, WorkStream™ and SiView™.  A key feature of this module is that it permits drill down from problems found in other data domains to the tool or tool group which may be the source of the problem, thereby saving significant fab engineering time in diagnosing yield problems.

 

YieldProjector

 

YieldProjector enables design engineers to improve their design’s projected yield before it reaches the manufacturing process. YieldProjector simulates the yield impact of a wide-range of random defects on a design’s layout based on statistical information from the manufacturing process.  YieldProjector reports the number of fatal defects on each layer of the design along with the projected yield of that layer.  YieldProjector graphically highlights yield-limiters in the design layout so design engineers can compare various layout options and critical feature usage to improve a design’s immunity to random and systematic manufacturing defects.  This significantly increases yield and speeds time to volume production.

 

TestChip Technologies Products and Services

 

Our TestChip products address the needs of semiconductor companies in many aspects of process technology development, design and manufacturing.  Developing process technology is typically a lengthy process that frequently takes 18-24 months and requires a number of expert resources to design and validate each process step followed by process qualification.  The complexity of smaller chip features, such as 90 nm and 65 nm (known as “nodes”), requires a large number of devices and circuits to measure not only each process step but also the integrated process behavior and performance.  This increasing complexity, coupled with smaller chip sizes, is causing semiconductor producers to turn to yield solutions such as those offered by our TestChip products.

 

HPL’s TestChip products provide capabilities to accelerate semiconductor process technology development to the 65nm node and beyond.  Additionally, for advanced technology nodes, TestChip products provide new and innovative methods for semiconductor manufacturing process characterization and monitoring.  We have deployed advanced semiconductor process technologies using our TestChip solutions at leading Integrated Device Manufacturers.  Semiconductor manufacturers have used TestChip solutions for more than 8 years, at 7 technology nodes and across multiple process technologies, such as CMOS, BiCMOS, Radio Frequency (“RF”), Analog and others.

 

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The TestChip product line consists of a library of proprietary intellectual property (“IP”), supplemented by software products, and services, each of which are described more fully below.  HPL will also customize the TestChip Technology IP and services to better enable project success.

 

TestChip Technology Development IP

 

Our proprietary TestChip IP contains over 1,500 elements to address the full breadth of 90nm CMOS technology development concerns, including 193nm lithography, copper and low-k interconnect integration, and advanced transistor development.  Our TestChip IP also contains elements for improving yield in test structures, non-volatile memory, Silicon-on-Insulator (“SOI”), high-power devices, Silicon-Germanium, and RF devices.  From this IP, we can produce GDSII, HTML documentation and test programs, all generated from a common database resulting in consistent and error-free results.

 

TestChip TechXpress Array Product Family

 

Our TestChip TechXpress array products alleviate many issues involved in sub-130nm technology development and monitoring. Traditional methods allow a limited number of devices and circuits to be used for identifying and resolving process and yield issues.  Our TechXpress array products dramatically increase the number of devices and circuits that can be used, thereby resulting in more effective identification, diagnosis and resolution of process and yield issues.

 

The TechXpress Array Family comprises of three powerful products: TDSRAM^TM, TDROM^TM and TDAnalog^TM.

 

TDSRAM: The TechXpress TDSRAM can be used for bitcell development and process qualification. The TDSRAM bit is designed intentionally to measure key process parameters and is more sensitive to variations and yield issues than a conventional SRAM design. The TDSRAM can also be used to measure defect densities during volume manufacturing.

 

TDROM: The TechXpress TDROM measures process excursion and design rule skews making it ideally suited for process characterization and monitoring. The higher number of circuits built within a specific TDROM provide a dramatically better spatial resolution than possible with traditional test structures.

 

TDAnalog: The TechXpress TDAnalog is unique in its ability to measure the intrinsic electrical properties of the process. It outputs a parametric response providing a finer resolution of the measurement. Examples of TDAnalog usage are via resistance measurements and FET matching effects measurements among others.

 

Some of the specific use cases for the array family products are bitcell development, process qualification, systematic yield loss diagnosis, process characterization and process monitoring. Customers use results derived from the arrays to correlate yield, and analyze failures electrically and physically.

 

TestChip Design & Verification Platform

 

The TestChip Design & Verification Platform is used to accelerate the specification, design, test and debug of test structures and large technology development testchips. The platform consists of a web-based application for specifications capture, revision control and project management, a layout compiler, an HTML documentation & test program generator and a secure layout viewer integrated with the compiler and documentation.

 

SALES AND MARKETING

 

We rely on our direct sales force, distributors and sales agents to penetrate the semiconductor and flat panel display manufacturing markets.  Our direct sales efforts have focused primarily on licensing our software products and TestChip technologies to IDMs, foundries and fabless semiconductor design companies and flat panel display manufacturers.  Our direct sales force operates out of our headquarters in San Jose, California and our facilities in Boston, Massachusetts; Austin, Texas; Plano, Texas; Yokohama, Japan; Hsin Chu, Taiwan; Aix-en-Provence, France; and Singapore.

 

Our sales and marketing personnel also focus on developing our relationships with industry partners, which include semiconductor original equipment manufacturers (“OEMs”) who bundle our products in their hardware.  These joint-marketing relationships provide us with access to the customer bases of these OEMs.  We intend to continue to expand our industry partnerships in the future.

 

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RESEARCH AND DEVELOPMENT

 

The market for yield optimization is characterized by rapid technological development and product innovation.  We believe that timely development of new products and enhancements to existing products are necessary to maintain our competitive position.  Accordingly, we devote a significant portion of our human and financial resources to research and development programs and seek to maintain close relationships with customers to remain responsive to their needs.

 

The complexity of yield optimization requires expertise in physical integrated circuit (“IC”) design and fabrication as well as software development.  Today, we employ a staff of software development engineers focused on the development of yield-optimization software products.  Our team also encompasses a core group of engineers and technicians with extensive education, experience and expertise in the semiconductor domain.  Virtually every discipline associated with the lifecycle of an IC is represented at our company, including device physics, product design, product engineering, yield engineering, failure analysis engineering, fab management, process engineering and testing.

 

COMPETITION

 

The worldwide market for productivity-enhancement tools and systems for semiconductor companies is highly competitive and characterized by rapidly changing technologies.  We face direct competition from semiconductor companies that have developed or have the ability to develop their own proprietary yield-optimization tools and systems, as well as third-party providers of yield-management software and services.

 

We have found that the tools and systems against which our products and services most commonly compete are those that semiconductor companies have created in-house as part of a specific fabrication process or through a dedicated development group.  We must overcome a tendency that some producers may have to resist outside solutions.

 

The third-party providers that compete in the market for yield-optimization tools are, generally, divisions of larger semiconductor equipment OEMs, such as KLA-Tencor or relatively small private companies.  Additionally, PDF Solutions provides service-based solutions where HPL products can also be used.  The success of our business or other businesses like ours might prompt increased competition.  As a result, we must continue to improve existing products, develop new products and protect our innovations through intellectual property laws in order to continue to differentiate our product offering.

 

Significant factors in our target market’s choice of productivity-enhancement software include its performance, ease of use, reliability, price, compatibility with existing systems, installed base, and technical service and support.  While price is an important competitive factor, we believe that customers will choose the most effective productivity software, even if it is more expensive, because of the added profitability from better production yield.

 

INTELLECTUAL PROPERTY

 

Our future success and competitive position depends heavily upon our continued ability to develop new proprietary technology while protecting our existing intellectual property.  To protect our products and the underlying technology, and to prevent competitors from using our technology in their products, we use a combination of patents, trade secrets and copyrights.  As of March 31, 2003, we held four U.S. patents, expiring at different times between 2013 and 2019, and had twenty U.S. patent applications and ten foreign patent applications pending.  We expect that if granted, the duration of these patents will be 20 years from the date of filing the application.  We continue to vigilantly pursue U.S. and foreign patent filings.  We have additional patent applications that we are developing internally and may file in the future.

 

There is no assurance that any of our current or future patent applications will result in patents, and our existing or future patents may be circumvented, declared invalid or challenged as to scope or ownership.  For these and other reasons, we may not realize any competitive advantage from our existing patents and any patents that we may be granted in the future.  Furthermore, others may develop technologies that are similar or superior to our proprietary technologies or design around any patents that we may hold.  To the extent that others are able to obtain patents that overlap with our technologies or processes, we may be required to license these patents.  If we are unable to license these patents or obtain licenses on acceptable terms, we may need to alter our products or discontinue selling them altogether.  In addition, we have not secured patent protection in foreign countries and we cannot be certain that the steps we take to prevent misappropriation of our intellectual property abroad will be effective, or that the application of foreign laws to technology developed abroad will not adversely effect the validity or enforceability of our U.S. patents.

 

Much of our intellectual property has not been patented or is not patentable.  Accordingly, we have historically protected our non-patented intellectual property as a trade secret.  Trade secret protection is in many ways inferior to patent protection.  Others may

 

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reverse-engineer our non-patented technologies and lawfully use any underlying technology that is discovered in this process.  We typically enter into confidentiality agreements with prospective customers, distributors and business partners prior to disclosing material proprietary information.  These agreements prohibit unauthorized use and disclosure of our trade secrets and other proprietary information.  We currently require all of our employees to enter into similar agreements.  While we believe that these agreements provide a measure of protection of our intellectual property, they may be declared invalid or unenforceable, or we may not have the resources to seek enforcement in the event of a breach.  Additionally, courts only protect trade secrets from misappropriation to the extent that we have taken reasonable steps to protect the confidentiality of these trade secrets.  It is possible that a court would find our trade-secret protection practices inadequate and therefore declare portions of our trade secrets unprotected from misappropriation.

 

Much of our source code is written by programmers and engineers in the Republic of Armenia.  We generally rely on U.S. and Armenian copyright law and international treaties for protection of our software source code, software object code, training materials and user manuals created by our employees.  As of March 31, 2003, we have registered 14 copyrights with the U.S. Copyright Office.  While U.S. copyright law protects the expression of an idea, it does not protect the idea itself from copying.  As a result, others may be able to glean valuable concepts and methods from our copyrighted material and lawfully use these ideas and methods in a competing venture by simply changing the manner of expression.  In an effort to protect our software from misappropriation, we do not typically divulge our source code to customers or vendors, although we have placed our source code in escrow in connection with certain transactions.

 

EMPLOYEES

 

As of March 31, 2003, we employed approximately 267 employees worldwide with 99 in the United States, 142 in Armenia and 26 in five other locations around the world.  None of our employees are represented by a labor union or are subject to a collective bargaining agreement.  We believe that our relationship with our employees is good.

 

DIRECTORS AND OFFICERS

 

The following table sets forth the directors and officers of the Company, their ages and positions as of May 31, 2003:

 

Name		Age		Position
Cary D. Vandenberg		47		President and Chief Executive Officer
Michael P. Scarpelli		36		Chief Financial Officer, Treasurer, Senior Vice President of Administration and Assistant Secretary
Gene Mullinnix		51		Senior Vice President of Operations
Elias Antoun		46		Director, Chairman of the Board
Lawrence Kraus		40		Director
Dr. Yervant Zorian		47		Director
Michael J. Field		54		Vice President, General Counsel and Secretary
Robert B. Baden		60		Vice President of Global Sales
James Chalmers		43		Vice President of Marketing

 

CARY D. VANDENBERG.  Mr. Vandenberg joined the Company in May 2003 as President and Chief Executive Officer.  Prior to joining HPL, Mr. Vandenberg was Vice President of Strategic Business Development at Communicant Semiconductor Technologies AG, a European based semiconductor foundry.  He worked at Communicant from July 2001 to May 2003 and during this period he was responsible for the design kit and modeling group, corporate partnerships, and the e-business strategy.  Mr. Vandenberg has over 20 years of management experience in software and semiconductor companies including positions at Sequencia, Inc. (President & CEO), JENOPTIK INFAB Intrack, Inc. (President), and PROMIS Systems Corporation Ltd. (Vice President).  Mr. Vandenberg holds a Bachelor of Science degree in commerce from Santa Clara University.

 

MICHAEL P. SCARPELLI.  Mr. Scarpelli has been our Chief Financial Officer, Treasurer, Senior Vice President of Administration and Assistant Secretary since July 2002.  In these roles, he is principally responsible for the Company’s worldwide finance function including accounting, financial systems and facilities.  Mr. Scarpelli joined the Company in January 2002 as Vice President of Corporate Development, responsible for the oversight of the Company’s mergers and acquisitions function.  Prior to joining HPL, Mr. Scarpelli was an auditor with PricewaterhouseCoopers LLP since 1989 and an audit partner since 1998.  Mr. Scarpelli received his Bachelor of Arts degree in economics from the University of Western Ontario and is a Certified Public Accountant and a Chartered Accountant.

 

GENE MULLINNIX.  Mr. Mullinnix has been Senior Vice President of Operations since July 2002.  In this role, he is responsible

 

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for all aspects of product development and customer deployment and support.  Mr. Mullinnix has over 29 years of semiconductor industry experience including 9 years with Texas Instruments and 18 years with Motorola.  In February 2001, Mr. Mullinnix joined TestChip Technologies, Inc. (“TestChip”), as Vice President of Engineering.  Mr. Mullinnix joined HPL in February 2002 in connection with the Company’s acquisition of Covalar Technologies Group, Inc., the parent of TestChip, and was promoted to the position of President and General Manager, TestChip.  Prior to joining TestChip, Mr. Mullinnix worked for eighteen years in various positions at Motorola including Operations and Program Manager for the Non-Volatile Memories Technology Center, Site and Wafer Fab Operations Manager, and Global Technology Manager.  Mr. Mullinnix managed wafer fabs for Motorola in California and North Carolina with responsibilities in wafer fab operations, site management, technology development and a design center.  Mr. Mullinnix organized and developed the Microcontroller Technology Group’s External Manufacturing Operations establishing and managing foundry relationships in Asia, Japan, Europe and Israel.  Mr. Mullinnix holds a Bachelor of Science degree in Engineering from Texas A&M University.

 

ELIAS ANTOUN.  Mr. Antoun has served as President and Chief Executive Officer of MediaQ, Incorporated, a semiconductor manufacturer, since February 2000.  From March 1998 to January 2000, Mr. Antoun served as Executive Vice President, Consumer Products Division at LSI Logic.  Mr. Antoun served as President of LSI Logic K.K., a Japanese subsidiary of LSI Logic, from January 1996 to March 1998.  Mr. Antoun was elected to our board of directors in August 2000 and has served as the Chairman of the board since July 2002.  Mr. Antoun’s term expires at the next election of directors.

 

LAWRENCE KRAUS.  Mr. Kraus is a co-founder of the Company and has served as a member of the board of directors of the Company’s principal operating subsidiary, HPLI, since its formation in 1989.  From Feb