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UNITED STATES SECURITIES AND EXCHANGE COMMISSION
WASHINGTON, D.C. 20549
FORM 10-K
[X] ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE
ACT OF 1934 FOR THE YEAR ENDED OCTOBER 31, 2000
OR
[ ] TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES
EXCHANGE ACT OF 1934
COMMISSION FILE NUMBER 0-45138
SYNOPSYS, INC.
(Exact name of registrant as specified in its charter)
DELAWARE 56-1546236
(State or other jurisdiction of (I.R.S. Employer Identification No.)
incorporation or organization)
700 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA 94043
(Address of principal executive offices)
(650) 584-5000
Registrant's telephone number, including area code
SECURITIES REGISTERED PURSUANT TO SECTION 12(b) OF THE ACT: NONE
SECURITIES REGISTERED PURSUANT TO SECTION 12(g) OF THE ACT:
Common Stock, $0.01 par value
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Preferred Share Purchase Rights
Indicate by check mark whether the registrant (1) has filed all reports
required to be filed by Section 13 or 15(d) of the Securities Exchange Act of
1934 during the preceding 12 months (or for such shorter period that the
registrant was required to file such reports), and (2) has been subject to such
filing requirements for the past 90 days.[X] Yes [ ] No
Indicate by check mark if disclosure of delinquent filers pursuant to
Item 405 of Regulation S-K is not contained herein, and will not be contained,
to the best of registrant's knowledge, in definitive proxy or information
statements incorporated by reference in Part III of this Form 10-K or any
amendment to this Form 10-K. [ ]
The aggregate market value of voting stock held by non-affiliates of the
registrant as of January 2, 2001, was approximately $2,314,010,470
On January 2, 2001, approximately 71,511,053 shares of the registrant's
Common Stock, $0.01 par value, were outstanding.
DOCUMENTS INCORPORATED BY REFERENCE
Portions of the registrant's Notice of Annual Meeting and Proxy
Statement for the registrant's annual meeting of stockholders to be held on
April 6, 2001 are incorporated by reference into Part III hereof.
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SYNOPSYS, INC.
ANNUAL REPORT ON FORM 10-K
YEAR ENDED OCTOBER 31, 2000
TABLE OF CONTENTS
PAGE NO.
PART I .................................................................................................... 3
Item 1. Business ........................................................................................ 3
Item 2. Properties ...................................................................................... 14
Item 3. Legal Proceedings ............................................................................... 14
Item 4. Submission of Matters to a Vote of Security Holders ............................................. 14
PART II ................................................................................................... 16
Item 5. Market for Registrant's Common Equity and Related Stockholder Matters ........................... 16
Item 6. Selected Financial Data ......................................................................... 16
Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations
Results of Operations ........................................................................... 17
Item 7A. Quantitative and Qualitative Disclosure About Market Risk ...................................... 27
Item 8. Financial Statements and Supplementary Data ..................................................... 28
Item 9. Changes in and Disagreements with Accountants on Accounting and Financial Disclosure ............ 51
PART III .................................................................................................. 51
Item 10. Directors and Executive Officers of the Registrant ............................................. 51
Item 11. Executive Compensation ......................................................................... 51
Item 12. Security Ownership of Certain Beneficial Owners and Management ................................. 51
Item 13. Certain Relationships and Related Transactions ................................................. 51
PART IV ................................................................................................... 51
Item 14. Exhibits, Financial Statements, Schedules and Reports on Form 8-K .............................. 51
SIGNATURES ................................................................................................ 55
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PART I
This Form 10-K, including "Item 1. Business," includes forward-looking
statements within the meaning of Section 21E of the Securities Exchange Act of
1934. These statements include, but are not limited to, statements concerning:
the Company's business strategy; the Company's plans to expand its consulting
services business; the Company's expansion into the market for physical design
tools; the Company's intention regarding its system level design and
verification tools; the Company's intention regarding design reuse tools and
techniques; the Company's expectations regarding research and development, sales
and marketing, and general and administrative expenses; the Company's efforts to
enhance its existing products and develop or acquire new products; and the
Company's requirements for working capital. The Company's actual results could
differ materially from those projected in the forward-looking statements as a
result of risks and uncertainties that include, but are not limited to, those
discussed under the caption "Factors That May Affect Future Results" under
"Management's Discussion and Analysis of Financial Condition and Results of
Operations" included in Part II, Item 8 hereto, as well as factors discussed
elsewhere in this Form 10-K.
ITEM 1. BUSINESS
INTRODUCTION
Synopsys, Inc. ("Synopsys" or the "Company") is a leading supplier of
electronic design automation (EDA) software to the global electronics industry.
The Company's products are used by designers of integrated circuits (ICs),
including system-on-a-chip ICs, and the electronic products (such as computers,
cell phones, and internet routers) that use such ICs to automate significant
portions of their chip design process. ICs are distinguished by the speed at
which they run, their area, the amount of power they consume and the cost of
production. The Company's products offer its customers the opportunity to design
ICs that are optimized for speed, area, power consumption and production cost,
while reducing overall design time. The Company also provides consulting
services to assist customers with their IC designs, as well as training and
support services. Synopsys was incorporated in Delaware in 1987.
THE ROLE OF EDA IN THE ELECTRONICS INDUSTRY
Over the past three decades, technology advances in the semiconductor
industry have dramatically increased the size, speed and capacity of ICs:
- The number of transistors that can be placed on a chip has doubled
roughly every 18 months. A state-of-the-art IC may hold over 20
million transistors. This is made possible in large part because the
width of the features on the chip is steadily shrinking. Most ICs
today are produced at 0.35 micron or 0.25 micron. Over the next
several years, the bulk of production will shift to 0.18 micron, and
then to 0.13 micron or below.
- The speed at which chips operate has steadily increased.
Microprocessors operating at 1.4 gigahertz, a speed that was unheard
of a few years ago, are available today.
- Chips are also becoming more economical in their power consumption,
which is necessary to drive more and more powerful handheld devices.
- Increasingly, functions that formerly were performed by multiple ICs
attached to a printed circuit board are being combined in a single
chip, referred to as a system-on-a-chip.
Combined, these changes have fostered the development of computers,
internet routers, wireless communications networks, hand-held personal digital
assistants, and many other goods and services with tremendous capabilities at
relatively low cost.
In the current economic environment, competition and continuing
innovation have shortened the life cycle of electronic products, so
time-to-market is crucial to the success of a product. Time to market can in
large part be determined by the time it takes to design the chip that will run
such product. EDA products play a critical role in reducing time-to-market for
new products by providing IC designers with tools and techniques to (a) reduce
the time and manual effort required to design, analyze and verify individual
ICs, (b) improve the performance and density of complex IC designs and (c)
enhance the reliability of the IC design and manufacturing process.
THE DESIGN PROCESS
In simplified form, the design of an integrated circuit consists of five
basic steps:
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System Design. First, a designer describes the functions that the chip
is to perform in a specialized high level computer language. During this phase,
designers perform high level architectural design tradeoffs, to determine, for
example, which algorithms to use to implement the design, and what portions of
the design to implement in hardware and what portions in software. At the
completion of this phase, the designer produces a "register transfer language"
or "RTL" description of the chip. Most of this process is completed manually,
although there is a small but growing market for products that help automate
design and verification at the system level.
Logic Synthesis. After the designer is satisfied with the RTL code, a
logic synthesis program converts the RTL code into a logical diagram of the
chip. Related programs insert the circuitry that will be required to test the
chip after manufacture. A "gate level" (so called because it describes the
various logic blocks, or gates, required to implement the chip) data file is
produced. In a growing number of designs, the logic synthesis phase is performed
together with a portion of physical design. This combined process, known as
"physical synthesis" produces a file containing "placed gates", which describes
the logic blocks and includes information about where they will be physically
located, or "placed", on a chip. See discussion below under "Current Issues
Facing IC Designers".
High Level Verification. At this stage the designer uses simulation and
related programs to verify that the design successfully performs the functions
that the designer intended, by feeding an exhaustive array of potential inputs
into a specialized program, "simulating" the functioning of the chip as
designed, and checking to confirm that the outputs match what was expected. The
designer also uses a timing analysis program to confirm that the chip as
designed will operate at the speed the designer intended.
Physical Design. If the designer is satisfied with the results of high
level verification, the transistors, and all of the wires connecting each one of
them, are mapped out in a series of transformations that gradually gets more and
more detailed. First the location on the chip die of each block of the chip and
each transistor within each block is determined -- a process known as
"placement" -- then all of the connections between the transistors are
determined -- a process known as "routing". The result is one or more data files
that can be read by physical verification programs (see below) or by the
equipment used to manufacture the chip.
Physical Verification. Before sending the design data file to a chip
manufacturer for fabrication, a further verification step is undertaken. The
designer must confirm that the chip as placed and routed will operate at the
speed anticipated during the logic design phase. The designer also must check
for unintended electrical effects that may arise as a consequence of placing
certain portions of the chip, or routing certain of its "wires", too close
together or in a bad position. Finally, the designer must verify that the final
design complies with all of the design rules set forth by the party that will
manufacture the chip.
The foregoing discussion has been greatly simplified. In the actual
design of a chip each of these steps has a number of different elements. The
steps, or the different elements within the steps, may be undertaken in a
different order or repeated one to multiple times. In any event, if at any stage
of the process the chip does not perform as intended, then the designer must go
back one or more steps to either redesign the RTL, redesign the logic, re-run
the verification or redo the physical design of the chip. Each iteration takes
time, and the more time the process takes, the more difficult it will be for the
designer to meet his or her time to market goals.
CURRENT ISSUES FACING IC DESIGNERS
As chip technology continues to advance, and particularly as the
state-of-the-art in chip design moves to 0.18 micron and below, Synopsys'
customers are facing a number of difficult design challenges:
Timing Closure. Ensuring that a chip will run at the desired speed
becomes substantially more difficult as transistor sizes move to 0.18 micron and
below. At larger transistor feature sizes, IC designers could use standard
estimates of chip timing during the logic design phase, and be confident that
the timing characteristics would be preserved through the physical design phase.
At 0.18 micron and below, these estimates become more and more unreliable. To
address this problem, customers will increasingly need products (referred to in
the EDA industry as "physical synthesis" products) that integrate logic design
and physical design. Synopsys physical synthesis solution takes physical design
information into account during logic design, and produces a file containing
"placed gates". Physical synthesis provides more accurate timing estimates at
the logic design phase and greatly improving the correlation between original
timing estimates after logic design and timing results after physical design.
Verification. Verification is the process of ensuring, at various stages
of the design process, that a chip will perform as intended. As the number of
transistors on a chip grows, the verification problem grows geometrically. In
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fact, with today's chips, verification often takes up the single largest
proportion of the overall design process. Verification products must offer
customers a combination of speed, accuracy and the ability to focus on the
portions of the chip most likely to cause problems.
Designer Shortage. Finding, hiring and retaining qualified design
engineers is often the most difficult problem that our customers face. Without
enough designers it is difficult for a company to meet ambitious development
schedules, and to get its products to market in a timely manner. Companies
address this shortage in a variety of ways, including seeking to import
designers from outside of the United States, locating development efforts
offshore and outsourcing all or parts of their design work. For EDA companies
the shortage of designers creates opportunities for companies that offer
pre-designed, pre-verified design "building blocks" that can be re-used in
multiple designs, and that offer professional services to augment their
customers design teams.
SYNOPSYS OVERVIEW
Synopsys provides products and services that help customers meet the
challenges of designing leading edge ICs and the products that incorporate them.
Synopsys offers a comprehensive suite of logic synthesis and related
products that allow an IC designer to describe chip behavior in a high-level
language and convert that description into a map of the logic implementing such
chip, including circuits that facilitate testing of the chip it is fabricated.
During fiscal 1999 and fiscal 2000, Synopsys has extended its design tools
product line to include several products targeted at the physical design portion
of the IC design process. Rather than producing a standalone physical design
product, Synopsys is focusing on physical synthesis products, which integrate
logic design and physical design. In fiscal 2000, Synopsys formally introduced
Physical Compiler, the principal product in our physical synthesis suite, which
integrates synthesis, placement and global routing.
Synopsys' high level and physical verification products are used by IC
designers in several stages of the IC design process to ensure that the
resulting IC performs the function that the designer intended. Synopsys'
simulation products permit IC designers to simulate their designs and to explore
tradeoffs between incorporating functionality in hardware or software. Synopsys
also offers a suite of products that help designers focus on the most
problematic portions of their chips. And to help customers analyze other aspects
of chip performance, Synopsys offers an extensive line of software tools to
analyze power, timing and reliability concerns in an IC design at the RTL, gate
and transistor level.
Synopsys provides the broadest array of reusable design building blocks
of any company in the EDA and intellectual property (IP) industry. The Company's
IP products also include software and hardware models, which are used to test an
IC design within the context of the system in which the IC will eventually be
used.
Synopsys also offers a full range of professional services to help
customers improve their internal design methodologies, as well as design
services ranging from specialized assistance to turnkey design.
Synopsys markets its products on a worldwide basis and offers
comprehensive customer service, education, consulting, and support as integral
components of its product offerings. Products are marketed primarily through its
direct sales force. Synopsys has licensed its products to most of the world's
leading semiconductor, computer, communications and electronics companies.
STRATEGY
Synopsys' strategy is to develop and offer to its customers a broad
array of tools and services required to enable design of complex ICs, especially
system-on-a-chip ICs. The Company is seeking to build on its current market
position to help customers address the most pressing problems of IC design at
0.18 micron and below: timing closure, verification, and the shortage of skilled
designers. First, building from its historical base of strength in high level
design, Synopsys plans to help customers address the timing closure problem by
continuing its expansion into the market for physical synthesis products --
products that integrate logical and physical design. Second, Synopsys will seek
to help customers address their verification needs by building a comprehensive
offering of verification products around its current position in simulation,
test and timing analysis. Third, Synopsys intends to help customers address the
designer shortage by expanding its inventory of reusable design building blocks,
which will allow customers to focus their own design teams on areas of
competitive differentiation, and by expanding its capacity to offer professional
services to supplement customers' own design teams.
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PRODUCTS
Synopsys products and services are focused on the principle needs of IP
and systems designers, and can be divided into five categories -- IC
Implementation, Verification and Test, IP and Systems Design, Transistor Level
Design and Professional Services. These products included in these categories
are discussed below. Financial information regarding these products is included
under Item 7 --Management's Discussion and Analysis of Financial Condition and
Results of Operation -- Results of Operation -- Revenue -- Product Groups".
IC Implementation Products
Synopsys' IC Implementation products include the Company's basic logic
synthesis and related products, and the Company's new physical synthesis
products.
During fiscal 2000, IC Implementation products accounted for 39% of the
Company's revenues.
Logic synthesis is the process by which a high-level description of
desired chip functions is mapped into a connected collection of logic gates and
other circuit elements that performs the desired functions. Design Compiler(TM)
is the market-leading logic synthesis tool and is used by a broad range of
companies engaged in the design of ICs to optimize their designs for performance
and area. Design Compiler was introduced in 1988 and has been updated regularly
since then. The Company's Design Compiler product family also includes Power
Compiler and Module Compiler. Power Compiler provides "push-button" power
optimization and early analysis for the design of low power circuits, which are
key for the design of hand-held devices. Module Compiler is used in the design
of complex datapaths.
In fiscal 2000, Synopsys released Design Compiler(TM) 2000 as the latest
generation in the Design Compiler family. Design Compiler 2000 features
significant enhancements, including integration of datapath synthesis technology
from the Company's Module Compiler product, enhanced design-for-test
capabilities, and improved quality of results. In the Company's physical
synthesis suite of products, Design Compiler will continue to be used for
synthesis of non-timing-critical portions of a design.
Physical synthesis unites logic synthesis, placement and top level
routing and links them together with common timing. When used together, the
physical synthesis suite of products provides customers with an integrated
design flow from register transfer level (RTL) through placement and top level
routing, and addresses the critical timing problems encountered in designing
advanced ICs and systems-on-a-chip. In fiscal 2000, Synopsys formally released
Physical Compiler, a next-generation product aimed at designing ICs at 0.18
micron and below. Physical Compiler unifies synthesis and placement into a
single product to provide high-quality timing closure capability for the
individual blocks large IC designs. Physical Compiler is marketed to customers
as an upgrade to Design Compiler, and shares with Design Compiler a common
database, user model, constraints, timer and libraries.
As of January 15, 2001, Physical Compiler had been licensed to over 70
customers and more than 70 IC designs had been completed using Physical
Compiler. During fiscal 2000 the Company received approximately $57 million in
orders for Physical Compiler.
The physical synthesis suite of products also includes Chip Architect
and FlexRoute. Chip Architect is a hierarchical design planner, which takes into
account physical phenomena and is used at various stages of the system-on-a-chip
design process to perform chip-level estimation, floor-planning, timing analysis
and placement. FlexRoute is a high-capacity, object-based, top-level router,
which is used to route the longest, most-difficult-to-route connections between
functional blocks on a system-on-a-chip. FlexRoute is "object-based" and permits
true gridless routing, which enables chip designers to address issues such as
cross-talk, delay and signal integrity, while optimizing chip area.
The Company's IC Implementation products also include logic synthesis
products for field programmable gate arrays (FPGAs) and complex programmable
logic devices (CPLDs). With the advent of high-density chips (.25 micron and
below), FPGAs have become fast enough to handle a substantial fraction of
projects that previously required mask-programmed application specific
integrated circuits (ASICs). Furthermore, FPGAs' unique ability to deliver very
quick time-to-market make them attractive in today's business environment. In
fiscal 2000, Synopsys announced new versions of FPGA Express(TM) and FPGA
Compiler II(TM).
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Verification and Test Products
The Company's Verification and Test products consist of a group of
tools, including simulation, test automation and timing verification products,
to enable IC designers to quickly and reliably verify the behavior of a design
before it is committed to the expensive and time-consuming process of IC
fabrication, and to assist in the testing of the chip after manufacturing.
During fiscal 2000, Verification and Test products accounted for 30% of
the Company's revenues.
Simulation and related products. Simulation software "exercises" an IC
design by running it through a series of tests and comparing the actual outputs
from the design with the expected output. As such, simulation products are the
key products for functional verification. The goal of simulation is to make sure
that the functionality and timing performance of the design meets the original
specifications of the chip. Synopsys offers two products for high-level
simulation: VCS(TM), for designs written in Verilog (one of the two principal
register transfer languages) and Scirocco(TM), for designs written in VHDL (the
other principal RTL). Simulation products are distinguished principally by their
runtime -- i.e., how fast they can fully simulate a proposed design. The Company
is focused on providing the industry's fastest simulation technology and
believes that both VCS and Scirocco are industry leaders in performance and
capacity. VCS is supported by all major semiconductor manufacturers and many
third-party EDA software providers.
In addition to focusing on building the fastest simulator, Synopsys is
focused on developing a suite of products that help simulation products work
"smarter." The Company estimates that more time is spent in writing verification
testbenches than in creating the design description. Testbenches, which create
stimuli for chips and check the results, are used in conjunction with simulation
tools to verify that a design functions as expected. The Verification Technology
group provides software that helps generate and manage testbenches as well as
evaluate the effectiveness of the simulation process. VERA(R) is a tool that
automates the design of testbenches, thereby offering the IC designer
significant reductions in overall design and verification time. VERA provides a
high-level language designed specifically for verifying complex designs. VERA is
integrated with the Company's other simulation, modeling and hardware/software
co-verification products. The Company's CoverMeter product enables designers to
measure the effectiveness of their testbenches to ensure that all aspects of the
design is tested. CoverMeter is tightly integrated with VCS.
Test Automation. In order to meet today's stringent quality
requirements, chips must pass through rigorous testing after manufacturing.
Synopsys' design-for-test (DFT) tools offer a complete DFT solution. Synopsys'
DFT Compiler, the industry-standard 1-pass test synthesis product, inserts all
functional and test logic required to enable efficient, high-coverage testing of
the chip after manufacturing, while complying with the customer's design rules
and constraints (timing, area, power, etc.). DFT Compiler works seamlessly with
Design Compiler and Physical Compiler, with the added benefit, in the case of
Physical Compiler, of placement-driven optimization of test logic. In January
2001 DFT Compiler was awarded the 2001 "Best in Test" Award from Test &
Measurement World, an industry journal. The award is presented annually to honor
important and innovative new products in the electronics test and measurement
industry.
Automatic test pattern generation (ATPG) is the other component of
Synopsys' complete DFT solution. TetraMAX(TM) ATPG, the Company's ATPG product
is optimized for ease-of-use, capacity, speed, coverage and vector compaction.
TetraMAX ATPG works in concert with DFT Compiler to enable total automation of
the DFT flow. Synopsys test methodology also includes software to facilitate the
failure diagnosis of chips after manufacturing test, expediting the
time-consuming and expensive post-fabrication activities required to determine
the cause of manufacturing defects. TetraMAX ATPG was also awarded the 2000
"Best in Test" award from Test & Measurement World.
Static Timing Analysis. Synopsys provides a complete tool suite to help
designers perform static timing analysis at the gate- and transistor levels and
analyze signal integrity issues such as cross-talk. Synopsys' gate-level
analysis tool is called PrimeTime(R). PrimeTime is a full-chip, gate-level
static timing analysis tool targeted for complex multimillion gate designs,
which is used by designers to verify, at various stages of the design process,
the speed at which a design will operate when it is fabricated. PrimeTime's
analysis of a design's speed is accepted as a "sign off" tool by virtually all
major semiconductor manufacturers, which means that they accept its analysis as
determinative. (Synopsys transistor-level timing analysis products are described
below under "Transistor Level Design".
Formal Verification -- Equivalence Checking. Formal verification is a
method for comparing two versions of a design to determine if they are
equivalent. Usually an RTL version of the design is validated using simulation
and other dynamic verification tools, establishing it as the golden version.
Subsequent versions (i.e., after each step of the design process) are then
compared to the golden version, using mathematical algorithms, to determine if
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they are functionally equivalent. The use of formal verification greatly reduces
the need to perform simulation, which is substantially more time-consuming, at
each stage of the design process, thus potentially saving a significant amount
of time in the overall design process. Synopsys' formal verification product is
Formality(R). Formality was one of the industry's first commercial equivalency
checkers to employ a multi-solver architecture, which enables the verification
of complex multimillion-gate system-on-a-chip designs in days or minutes.
Intellectual Property (IP) and Systems Products
The Company's IP and Systems products include our DesignWare, models,
and systems design and verification products.
During fiscal 2000, IP and Systems products accounted for 14% of the
Company's revenues.
Intellectual Property Products. As IC designs continue to grow in size,
reusing design blocks is becoming a more important method for reducing overall
design cycle time. By reusing portions of a design, and particularly those that
implement basic or standardized functions, a company can let its IC design team
focus on designing the chip features that will give its product a competitive
advantage. It can also reduce it's verification risk by ensuring that these
portions of the chip are of high quality. Enabling reuse of intellectual
property (IP) requires a significant methodology shift from traditional IC
design. In the past, designs were intimately tied to a particular semiconductor
process technology or design methodology, making reuse of design blocks from one
chip design to the next difficult and costly.
Synopsys' DesignWare(R) product provides IC designers with libraries of
pre-designed, pre-verified Synopsys-synthesizable (i.e., usable by Synopsys'
design tools in optimizing a design), off-the-shelf design modules to
incorporate into their own designs. The DesignWare foundation library includes
more than 100 commonly used functions of low- to medium-scale complexity,
including an 8051 microcontroller block and a PCI 2.1 bus interface block.
DesignWare Developer helps customers package their own low-complexity functions
so that they are integrated into designs in the same way as DesignWare
components.
The Company's IP and Systems products also include high-level models and
tools to facilitate the modeling and verification of complex electronic systems.
Synopsys offers a full range of hardware and software modeling solutions.
ModelSource(TM) 3000 series is a family of hardware modeling systems for ASIC
and board level design which provide a flexible means for designers to model
complex devices. ModelSource 3000 systems use the actual integrated circuit to
model its own behavior in a larger system. Synopsys' SmartModels(R) Libraries
offer models for more than 18,000 commercially available ICs, including a wide
range of microprocessors, controllers, digital signal processors, FPGAs, CPLDs,
peripherals, memories and standard logic. Synopsys' bus interface models are
used to verify that designs comply with established industry standards. Starting
in fiscal 2001, these models and the SmartModels libraries will be offered
exclusively with DesignWare. In addition, Synopsys offers modeling technologies
to allow designers to create models of both standard and proprietary devices.
These models support all major EDA simulation environments and a wide range of
EDA platforms, giving designers access to a broad range of models to assist them
with verification of their designs.
Systems Design and Verification Products. Currently, automated design
generally begins at the RTL level, with logic synthesis. The goal of
"system-level" products is to permit designers to design and verify their
products at a level of abstraction above RTL. Synopsys' systems products
consist of the CoCentric(TM) family of tools and methodologies for concurrent
design, validation, refinement and implementation of an electronic system.
The CoCentric family of products are based on a new language named
"SystemC" developed by Synopsys and now available under an open source license.
SystemC enables designers to create, validate and share system level models of a
complex IC or system incorporating the chip, and therefore can be used to
explore and verify design alternatives at an early stage of the design process.
In addition, EDA vendors have complete access to the SystemC modeling platform
required to build interoperable tools. SystemC is managed by the Open SystemC
Initiative, which includes representation from the systems, semiconductor, IP,
embedded software and EDA industries. The steering group is composed of ARM,
Cadence Design Systems, CoWare, Ericsson, Fujitsu Microelectronics, Infineon
Technologies, Lucent Technologies, Motorola, NEC, Sony, STMicroelectronics,
Texas Instruments and Synopsys.
The Company has introduced two products based on SystemC. CoCentric
System Studio is a system-level design environment for the rapid creation of
executable system specifications that can be verified and implemented as
hardware and software functions. System Studio enables designers to use
hierarchical graphical and language modeling to capture system complexity in a
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unified environment based on C, C++ and SystemC. System Studio supports
verification of hardware and software design refinements through concurrent
execution of C-based specifications, popular hardware simulators, and a variety
of processor models. In fiscal year 2000, Synopsys started to migrate customers
of its COSSAP(R) design system to CoCentric System Studio.
CoCentric SystemC Compiler is a synthesis tool that allows designers to
implement complex circuits from SystemC, enabling design to progress from an
initial C/C++ executable specification. Starting from a higher level of
abstraction than Design Compiler and eliminating the need to remodel in Verilog
or VHDL, SystemC Compiler accelerates the design cycle. SystemC Compiler allows
designers to rapidly create alternative implementations of a design, enabling
them to spend time productively evaluating tradeoffs in performance, size and
power consumption before committing to a particular implementation. CoCentric
SystemC is undergoing evaluation by a number of customers.
In fiscal 2000, the Company's IP and Systems products included silicon
libraries of logic functions used in developing ICs. On December 4, 2000, the
Company entered into an agreement to sell this business to Artisan Components,
Inc. The transaction closed in January 2001.
Transistor Level Design Products
Synopsys' transistor level design products include a range of products
in the areas of timing analysis and verification; power management; circuit
simulation and IP verification. These products, which are used after the
completion of physical design, help customers analyze the increasingly important
electrical effects resulting from designing at 0.18 micron and below, and to
locate implementation errors that can be costly and time-consuming to correct
during or after production. As the logic and physical design phases of IC
Implementation grow more and more integrated, the Company is also integrating
many of its transistor level design products with its high level verification
products, particularly in the areas of timing and power analysis.
During fiscal 2000, Transistor Level Design products accounted for 7% of
the Company's revenues.
Static Timing Analysis and Signal Integrity. As part of it's overall
approach to timing and signal integrity analysis and verification, Synopsys'
offers PathMill(R), PathMillPlus and AMPS(R). These tools are integrated with
Arcadia, the Company's resistance and capacitance (RC) extraction tool. The
tools enable quick identification and debugging of complex timing problems
taking into account signal integrity (not yet released) effects for ICs designed
at 0.18 micron and below. PathMill is a transistor-level static timing analysis
tool for designers of large, complex and high performance microprocessor and
DSPs. PathMillPlus is the next generation IP characterization product that
incorporates the capabilities of PathMill and delivers a comprehensive solution
for IP characterization and re-use.
Circuit Simulation. TimeMill(R) and PowerMill(R) provide high accuracy,
high speed, and high capacity circuit simulation technology. These tools are
vital in the diagnosis of design flaws in transistor-level blocks, including the
critical memories, datapaths, and analog/mixed-signal blocks, and assist
designers with the overall optimization of circuit speed and power dissipation.
Power Management. Synopsys delivers a complete solution to help
designers manage and verify power consumption at different levels of the design
process. The products in the solution include: Power Compiler (described under
IC Implementation category), PrimePower, PowerArc, PowerMill and RailMill.
PrimePower, introduced in fiscal 2000, is a dynamic, full-chip comprehensive
power analysis tool for complex multimillion-gate ASICs. PrimePower allows users
to quickly and efficiently verify that their IC designs meet power budgets and
specifications, select the proper packaging, determine cooling requirements and
estimate the battery life for portable applications. As a foundation for
Synopsys' power solution, PowerArc delivers automatic cell library power
characterization, making it easy for library providers and ASIC and silicon
vendors to automatically produce power libraries with SPICE-level accuracy.
Synopsys Professional Services Business Unit
Synopsys Professional Services provides a comprehensive portfolio of
consulting services covering all critical phases of the system-on-a-chip
development process, as well as systems development in wireless and broadband
applications. Customers are offered a variety of engagement models ranging from
project assistance - which helps a customer design, verify and/or test its chips
and improve its design process -- to full turn-key development.
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During fiscal 2000, the Synopsys Professional Services business unit
accounted for 10% of the Company's revenues.
Internet Design Services Business Unit
Through its DesignSphere(SM) Access program, the Internet Design
Services group provides a complete design environment for complex IC development
accessible over the internet. This service enables customers to use software of
the Company and others remotely without incurring the time and costs of
installing, owning and maintaining the software and associated hardware. The
software is available on custom-configured, dedicated, high-performance computer
hardware, protected by physical and software security measures including
firewalls, bi-directional data encryption and custom access protocols. Security
is audited by third-party experts, and the Company provides backup and disaster
recovery services.
ORGANIZATION
Synopsys is currently organized into four product development groups --
Physical Synthesis, Verification Technology, Intellectual Property and Systems,
and Nanometer Analysis and Test -- and a services group -- Synopsys Professional
Services. The Physical Synthesis business unit principally develops and manages
our IC Implementation products. The Verification Technology business unit
develops and manages the simulation products in our Verification and Test
product portfolio. The Intellectual Property and Systems business unit develops
and manages all of the product in the IP and Systems product category. The
Nanometer Analysis and Test business unit develops and manages the timing
analysis, power and test products in the Verification and Test product category,
and the products in the Transistor Level Design category.
During fiscal year 2000 Synopsys established a business unit -- the
Internet Design Services Business Unit -- to develop an "application service
provider" or "hosted design environment" business for the Company's software
products.
CUSTOMER SERVICE AND SUPPORT
Synopsys devotes substantial resources to providing customers with
technical support, customer education, and consulting services. The Company
believes that a high level of customer service and support is critical to the
adoption and successful utilization of high-level design automation methodology.
In Fiscal 2000, service revenue as a percentage of total revenue increased to
44% as compared to 37% in fiscal 1999.
TECHNICAL SUPPORT
Technical support for the Company's products is provided through both
field- and corporate-based technical application engineering groups. Synopsys
provides customers with software updates and a formal problem identification and
resolution process through the Synopsys Technical Support Center. Synopsys'
central entry point for all customer inquiries is SolvNET(R), a direct-access
service available worldwide, 24 hours per day, through electronic mail and the
World Wide Web that lets customers quickly seek answers to design questions or
more insight into design problems. SolvNET combines Synopsys' complete design
knowledge database with sophisticated information retrieval technology. Updated
daily, it includes documentation, design tips, and answers to user questions.
CUSTOMER EDUCATION SERVICES
Synopsys offers workshops focused on many aspects of high-level design
languages, high-level design, simulation, synthesis, physical design, system
design and test. Regularly scheduled workshops are offered in Mountain View,
California; Austin, Texas; Burlington, Massachusetts; Reading, England; Rungis,
France; Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other
locations. On-site workshops are available on a worldwide basis at customers'
facilities or in their locales. Over 15,000 design engineers attended Synopsys
workshops during fiscal 2000.
PRODUCT WARRANTIES
Synopsys generally warrants its products to be free from defects in
media and to substantially conform to material specifications for a period of 90
days. Synopsys has not experienced significant returns to date.
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SUPPORT FOR INDUSTRY STANDARDS
Synopsys actively supports standards that it believes will help its
customers increase productivity and solve design problems, including key
interfaces and modeling languages that promote system-on-a-chip design and
facilitate interoperability of tools from different vendors. Standards in the
EDA industry can be obtained through formal accredited committees, by licensing
made available to all, or through community licensing.
Synopsys' products support many formal standards, including the two most
commonly used hardware description languages, VHDL and Verilog HDL, and industry
standard data formats for the exchange of data between Synopsys' tools and other
EDA products.
Synopsys is a board member and/or participant in the major EDA standards
organizations: Virtual Socket Interface Alliance (VSIA), an industry group
formed to promote standards that facilitate the integration and reuse of
functional blocks of intellectual property; Accellera, a not-for-profit
consortium formed from the union of VHDL International and Open Verilog
International to drive language-based standards for systems, semiconductor, and
design tools companies; the EDIF steering committee of the Electronics Industry
Association (EIA), which evolves the Electronic Design Interchange Format
(EDIF); and the interoperability committee of the EDA Consortium, which helps
promote interoperability among EDA products from different vendors.
Synopsys' TAP-In program provides open access for all companies to
selected interfaces for Synopsys tools. Synopsys has licensed its text-based
synthesis library format, Liberty, as well as its design constraints format,
SDC, to the majority of the EDA industry, including the Company's competitors,
on reasonable terms. Synopsys has licensed to certain EDA companies its VERA API
(application programming interface) and VERA HVL (High-level Verification
Language) for test bench verification and its OpenESPF format for representing
physical data necessary for reliability verification.
SystemC, an open industry standard language for the exchange of
intellectual property and executable specifications, is discussed above under
"IP and Systems Business Unit."
Synopsys' products are written mainly in the C and C++ languages and
utilize industry standards for graphical user interfaces. Synopsys' software
runs principally under the UNIX operating system, with some products running
under Windows NT and many on Linux. Synopsys' products are offered on the most
widely used workstation platforms, including those from Sun Microsystems,
Hewlett-Packard, IBM, and Compaq (formerly Digital Equipment Corporation).
SALES, DISTRIBUTION AND BACKLOG
Synopsys markets its products and services primarily through its direct
sales and service force in over 30 offices in the United States and principal
international markets. Synopsys employs highly skilled engineers and technically
proficient sales persons, as required to understand our customers needs and to
explain and demonstrate the value of Synopsys' products.
For fiscal years 2000, 1999 and 1998, international sales represented
42%, 34% and 39%, respectively, of Synopsys' total revenue. For the one-month
period ended October 31, 1999, international sales represented 36% of the
Company's total revenue. Additional information relating to domestic and foreign
operations is contained in Note 8 of Notes to Synopsys' Consolidated Financial
Statements.
The Company has 23 sales/support centers throughout the United States,
in addition to its Mountain View, California headquarters. Internationally, the
Company has sales/support offices in Canada, Denmark, Finland, France, Germany,
Hong Kong, India, Israel, Italy, Japan, Korea, the People's Republic of China,
Singapore, Sweden, Taiwan and the United Kingdom, including international
headquarters offices in Ireland. On a limited basis, the Company also utilizes
manufacturer's representatives and distributors. The Company has established
such relationships in Australia, Brazil, China, India, Korea, Malaysia, and
Taiwan.
Synopsys' backlog on December 1, 2000 was approximately $462.8 million,
compared to approximately $276.0 million on December 1, 1999.
Backlog consists of orders for system and software products sold under
perpetual and time-based licenses with customer requested ship dates within
three months but which have not been shipped, orders for customer training and
consulting services which are expected to be completed within one year, and
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subscription services, maintenance and support with contract periods extending
up to fifteen months. In the case of a Technology Subscription License (TSL),
including a multiyear TSL, backlog includes the full amount of the order, less
any amount of revenue that has been recognized on such TSL.
The Company has not historically experienced significant cancellations
of orders. Customers frequently reschedule or revise the requested ship dates of
orders however, which can have the effect of deferring recognition of revenue
for these orders beyond the expected time period.
RESEARCH AND DEVELOPMENT
The Company's future performance depends in large part on its ability to
maintain and enhance its current product lines, develop new products, maintain
technological competitiveness, and meet an expanding range of customer
requirements. In addition to research and development conducted within each
business unit, the Company maintains an advanced research group that is
responsible for exploring new directions and applications of its core
technologies, migrating new technologies into the existing product lines, and
maintaining strong research relationships outside the Company within both
industry and academia.
During fiscal years 2000, 1999 and 1998, research and development
expenses, net of capitalized software development costs, were $189.3 million,
$167.1 million and $156.7 million, respectively. For the one-month period ended
October 31, 1999, research and development expenses were $17.2 million. Synopsys
capitalized software development costs of approximately $1.0 million, $1.0
million and $2.1 million in fiscal 2000, 1999 and 1998, respectively. For the
one-month period ended October 31, 1999, capitalized software development costs
were not material. The Company anticipates that it will continue to commit
substantial resources to research and development in the future.
MANUFACTURING
Synopsys' manufacturing operations consist of assembling, testing,
packaging and shipping its system and software products and documentation needed
to fulfill each order. Manufacturing is currently performed in Synopsys'
Mountain View, California, Beaverton, Oregon and Dublin, Ireland facilities.
Outside vendors provide tape and CD-ROM duplication, printing of documentation
and manufacturing of packaging materials. Synopsys employees manufacture and
test the hardware modeling system products, with some sub-assembly performed by
outside vendors. Synopsys typically ships its software products within 10 days
of acceptance of customer purchase orders and execution of software license
agreements, unless the customer has requested otherwise. On customer request,
Synopsys delivers its software products through electronic means rather than
shipping disks. This method of delivery is becoming increasingly common for
domestic customers. For its hardware modeling products, Synopsys buys components
and assemblies in anticipation of orders and configures units to match orders,
typically shipping within one to ten weeks of order acceptance, unless the
customer has requested otherwise.
COMPETITION
The EDA industry is highly competitive. We compete against other EDA
vendors, and with customers' internally developed design tools and internal
design capabilities, for a share of the overall EDA budgets of our potential
customers. In general, competition is based on product quality and features,
post-sale support, price and, as discussed below, the ability to offer a
complete design flow. Our competitors include companies that offer a broad range
of products and services, such as Cadence, Mentor Graphics and Avant!, as well
as companies, including numerous start-up companies, that offer products focused
on a discrete phase of the integrated circuit design process. In certain
situations, Synopsys' competitors have been offering aggressive discounts on
certain of their products, in particular simulation and synthesis products. As a
result, average prices for these products may fall. In order to compete
successfully, we must continue to enhance our products and bring to market new
products that address the needs of our customers. We also will have to expand
our consulting services business. The failure to enhance existing products,
develop and/or acquire new products or expand our ability to offer consulting
services could have a material adverse effect on our business, financial
condition and results of operations.
Technology advances and customer requirements continue to fuel a change
in the nature of competition among EDA vendors. Increasingly, EDA companies
compete on the basis of "design flows" involving integrated logic and physical
design products (referred to as "physical synthesis" products) rather than on
the basis of individual "point" tools performing a discrete phase of the design
process. The need to offer physical synthesis products will become increasingly
important as ICs grow more complex. Our main physical synthesis product was
fully released in June 2000, and has been well-received by customers, but we
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still do not offer customers a complete design flow. We are working on
completing our design flow, although there is no guarantee that we will be able
to offer a competitive flow to customers. The market for physical design tools
is dominated by Cadence and Avant!, both of which offer products linking logic
and physical design. If we are unsuccessful in developing a complete design flow
on a timely basis or in convincing customers to adopt our integrated logical and
physical design products and methodology, our competitive position could be
significantly weakened.
PRODUCT SALES AND LICENSING AGREEMENTS
Synopsys typically licenses its software to customers under
non-exclusive license agreements that transfer title to the media only and that
restrict use of the software to specified purposes within specified geographical
areas. The Company currently licenses the majority of its software as a network
license that allows a number of individual users to access the software on a
defined network. License fees are dependent on the type of license, product mix
and number of copies of each product required.
Synopsys currently offers its software products under either a perpetual
license or a shorter-term subscription license. Under a perpetual license a
customer pays a one time license fee for the right to use the software. The vast
majority of customers also purchase annual software support services, under
which they receive minor enhancements to the products developed during the year,
bug fixes and technical assistance. A subscription license, and the various
forms of time-based licenses that the Company has offered before introducing
subscription licenses, operates like a rental of software. A customer pays a fee
for license and support over a fixed period of time, and at the end of the time
period the license expires unless the customer pays for a renewal. Subscription
licenses are offered with a range of terms; the average length is approximately
three years. See "Management's Discussion and Analysis of Financial Condition
and Results of Operations --Results of Operations-Revenue."
Over the past several years, orders for time-based licenses (now
subscription licenses) have increased significantly as a percentage of total
product orders. During fiscal year 2000, orders for time-based licenses
accounted for 74% of total product orders compared to 64% in fiscal 1999 and
111% in fiscal 1998.
During fiscal year 2001 Synopsys expects that orders for subscription
licenses will account for approximately 75% of total product orders and orders
for perpetual licenses approximately 25% of total product orders, although there
are likely to be variations of plus or minus five percentage points in any
particular quarter.
Synopsys offers its hardware modeler products for sale or lease.
PROPRIETARY RIGHTS
The Company primarily relies upon a combination of copyright, patent,
trademark and trade secret laws and license and nondisclosure agreements to
establish and protect proprietary rights in its products. The source code for
Synopsys' products is protected both as a trade secret and as an unpublished
copyrighted work. However, it may be possible for third parties to develop
similar technology independently. In addition, effective copyright and trade
secret protection may be unavailable or limited in certain foreign countries.
The Company currently holds U.S. and foreign patents on some of the technologies
included in its products and will continue to pursue additional patents in the
future.
Although the Company believes that its products, trademarks and other
proprietary rights do not infringe on the proprietary rights of third parties,
there can be no assurance that infringement claims will not be asserted against
the Company in the future or that any such claims will not require the Company
to enter into royalty arrangements or result in costly and time-consuming
litigation.
EMPLOYEES
As of October 31, 2000, Synopsys had a total of 2,922 employees, of whom
2,098 were based in the United States and 824 were based internationally.
Synopsys' future financial results depend, in part, upon the continued service
of its key technical and senior management personnel and its continuing ability
to attract and retain highly qualified technical and managerial personnel.
Competition for such personnel is intense. Experience at Synopsys is highly
valued in the EDA industry, and the Company's employees are recruited
aggressively by competitors and by start-up companies, including those in
internet-related businesses. The Company's salaries are competitive in the
market, but under certain circumstances, start-up companies can offer more
attractive stock option packages. As a result, the Company has experienced, and
may continue to experience, significant employee turnover. There can be no
assurance that Synopsys can retain its key managerial and technical employees or
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that it can attract, assimilate or retain other highly qualified technical and
managerial personnel in the future. None of Synopsys' employees is represented
by a labor union. Synopsys has not experienced any work stoppages and considers
its relations with its employees to be good.
ITEM 2. PROPERTIES
Synopsys' principal offices are located in four adjacent buildings in
Mountain View, California, which together provide approximately 400,000 square
feet of available space. This space is leased through February 2003. Within one
half mile of these buildings, in Sunnyvale, California, Synopsys occupies
approximately 200,000 square feet of space in two adjacent buildings, which are
under lease through 2007, and approximately 85,000 square feet of space in a
third building, which is under lease until April 2007.
The Company currently leases approximately 14,000 square feet in Dublin,
Ireland, for its international headquarters and for research and development
purposes. This lease expires in May 2001, at which time the Company will execute
a 25-year lease for 45,000 square feet in a new facility in Dublin.
The Company leases approximately 93,000 square feet of space in
Beaverton, Oregon for administrative, marketing, research and development and
support activities. This facility is leased through March 2002, and will be
replaced by the newly constructed site in Hillsborough, Oregon.
In addition, the Company leases approximately 82,000 square feet of
space in Marlboro, Massachusetts for sales and support, research and development
and customer education activities. This facility is leased through March 2009.
The Company currently leases 23 other domestic sales offices throughout
the United States, as well as three remote locations. Synopsys currently leases
international sales and service offices in Canada, Finland, France, Germany,
Hong Kong, India, Israel, Italy, Japan, Korea, the People's Republic of China,
Singapore, Sweden, Taiwan, and the United Kingdom. The Company also leases
research and development facilities in France, Germany and India.
Synopsys owns a fourth building in Sunnyvale, with approximately 120,000
square feet, which is leased to a third party through May 2003. Synopsys also
owns thirty-four acres of undeveloped land in San Jose, California and 13 acres
of undeveloped land in Marlboro, Massachusetts. Additionally, Synopsys owns
forty-four acres of land in Hillsborough, Oregon on which two buildings,
totaling 236,000 square feet, are being constructed, with completion scheduled
for December 2001. This facility will replace the currently leased site in
Beaverton.
ITEM 3. LEGAL PROCEEDINGS
There are no material legal proceedings pending against the Company.
ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS
No matters were submitted for a vote of security holders during the
fourth quarter of the fiscal year covered by this Report.
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EXECUTIVE OFFICERS OF THE COMPANY
The executive officers of the Company and their ages, as of December 1,
2000, are as follows:
Name Age Position
- ---- --- --------
Aart J. de Geus 46 Chief Executive Officer and Chairman of the Board of Directors
Chi-Foon Chan 51 President, Chief Operating Officer and Director
Vicki L. Andrews 45 Senior Vice President, Worldwide Sales
Robert B. Henske 39 Senior Vice President, Finance and Operations, Chief Financial Officer
Steven K. Shevick 44 Vice President, Investor Relations and Legal, General Counsel
and Corporate Secretary
Dr. Aart J. de Geus co-founded Synopsys and currently serves as Chief
Executive Officer and Chairman of the Board of Directors. Since the inception of
Synopsys in December 1986 he has held a variety of positions including Senior
Vice President of Engineering and Senior Vice President of Marketing. From 1986
to 1992 Dr. de Geus served as Chairman of the Board. He served as President from
1992 to 1998. Dr. de Geus has served as Chief Executive Officer since January
1994 and has held the additional title of Chairman of the Board since February
1998. He has served as a Director since 1986. From 1982 to 1986, Dr. de Geus was
employed by General Electric Corporation, where he was the Manager of the
Advanced Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E. from
the Swiss Federal Institute of Technology in Lausanne, Switzerland and a Ph.D.
in electrical engineering from Southern Methodist University.
Dr. Chi-Foon Chan joined Synopsys as Vice President of Application
Engineering & Services in May 1990. Since April 1997 he has served as Chief
Operating Officer and since February 1998 he has held the additional title of
President. Dr. Chan also became a Director of the Company in February 1998. From
September 1996 to February 1998 he served as Executive Vice President, Office of
the President. From February 1994 until April 1997 he served as Senior Vice
President, Design Tools Group and from October 1996 until April 1997 as Acting
Senior Vice President, Design Reuse Group. Additionally, he has held the titles
of Vice President, Engineering and General Manager, DesignWare Operations and
Sr. Vice President, Worldwide Field Organization. From March 1987 to May 1990,
Dr. Chan was employed by NEC Electronics, where his last position was General
Manager, Microprocessor Division. From 1977 to 1987, Dr. Chan held a number of
senior engineering positions at Intel Corporation. Dr. Chan holds an M.S. and
Ph.D. in computer engineering from Case Western Reserve University.
Vicki L. Andrews joined Synopsys in May 1993 and currently serves as
Senior Vice President, Worldwide Sales. Before holding that position, she served
in a number of senior sales roles at Synopsys, including Vice President, Global
and Strategic Sales, Vice President, North America Sales and Director, Western
United States Sales. She has more than 18 years of experience in the EDA
industry. Ms. Andrews holds a B.S. in biology and chemistry from the University
of Miami.
Robert B. "Brad" Henske joined Synopsys in May 2000 and currently serves
as Senior Vice President and Chief Financial Officer. Mr. Henske joined Synopsys
from Oak Hill Capital Management, a Robert M. Bass Group private equity
investment firm where he was a partner from January 1997 to April 2000.
Additionally, Mr. Henske was Executive Vice President and Chief Financial
Officer, and a member of the board of directors of American Savings Bank, F.A.,
a Bass portfolio company from January 1996 to December 1996. Prior to that, he
was a business strategy and financial consultant for Bain & Company from
September 1988 to December 1995, where he last held the position of Vice
President. Mr. Henske received an MBA in finance and strategic management from
The Wharton School, University of Pennsylvania. He serves or has served on the
board of directors for several companies, including Grove Worldwide, L.L.C.,
Williams Scotsman, Inc., Reliant Building Products, Inc. and American Savings
Bank, F.A.
Steven K. Shevick joined Synopsys in July 1995 and currently serves as
Vice President, Investor Relations and Legal, General Counsel and Corporate
Secretary. From July 1995 to March 1998 he served as Deputy General Counsel and
Assistant Corporate Secretary. In March 1998 he was appointed Vice President,
Legal and General Counsel. In October 1999, Mr. Shevick gained the additional
title of Vice President of Investor Relations and was appointed Corporate
Secretary. Prior to joining Synopsys, Mr. Shevick was a lawyer in the New York,
Hong Kong and Washington, D.C. offices of Cleary, Gottlieb, Steen & Hamilton,
where his practice focused on international securities transactions, mergers and
acquisitions and technology licensing. Mr. Shevick holds an A.B. from Harvard
College and a J.D. from Georgetown University Law Center.
There are no family relationships among any executive officers of the
Company.
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PART II
ITEM 5. MARKET FOR REGISTRANT'S COMMON EQUITY AND RELATED STOCKHOLDER MATTERS
The information required by this item is set forth on page 50 of the
Synopsys 2000 Annual Report on Form 10-K.
ITEM 6. SELECTED FINANCIAL DATA
FINANCIAL SUMMARY
Fiscal Year One Month
Ended Ended Fiscal Year Ended September 30, (1) (2)
October 31, October 31, --------------------------------------------------------
(In thousands, except per share data) 2000(2) 1999(2) 1999 1998 1997 1996
- ------------------------------------- ----------- ----------- ----------- ----------- ----------- -----------
Revenue $ 783,778 $ 23,182 $ 806,098 $ 717,940 $ 646,956 $ 525,599
Income (loss) before income taxes and
extraordinary items (3) 145,938 (25,480) 251,411 116,861 132,793 40,228
Provision (benefit) for income taxes 48,160 (9,937) 90,049 55,819 51,043 23,426
Extraordinary items,
net of income tax expense -- -- -- 28,404 -- --
Net income (loss) 97,778 (15,543) 161,362 89,446 81,750 16,802
Earnings (loss) per share
Basic 1.43 (0.22) 2.30 1.34 1.30 0.28
Diluted 1.38 (0.22) 2.20 1.29 1.24 0.27
Working capital 331,857 621,918 627,207 504,759 336,675 238,942
Total assets 1,050,993 1,178,283 1,173,918 951,633 769,499 584,853
Long-term debt 564 11,304 11,642 13,138 9,191 15,974
Stockholders' equity 682,829 872,597 865,596 664,941 502,445 350,547
(1) Amounts and per share data for periods presented have been retroactively
restated to reflect the merger of Everest Automation, Inc. (Everest) in
a pooling-of-interests transaction effective November 21, 1998.
(2) The Company has a fiscal year that ends on the Saturday nearest October
31. Fiscal 2000, 1999, 1997 and 1996 were 52-week years while fiscal
1998 was a 53-week year. Fiscal year 2001 will be a 53-week year. For
presentation purposes, the consolidated financial statements and notes
refer to the calendar month end. Prior to fiscal 2000, the Company's
fiscal year ended on the Saturday nearest to September 30. The period
from October 3, 1999 through October 30, 1999 was a transition period.
Information for the transition period was filed with Synopsys' quarterly
report on Form 10-Q for the first quarter of fiscal 2000 and is included
in this annual report.
(3) Includes charges of $1.7 million, $21.2 million, $33.1 million, $5.5
million, $64.5 million, for the years ended October 31, 2000 and
September 30, 1999, 1998, 1997, and 1996, respectively, for in-process
research and development. Includes merger-related and other costs of
$51.0 million and $11.4 million for the years ended September 30, 1998
and 1997, respectively.
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ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS
OF OPERATIONS
The following discussion contains forward-looking statements within the
meaning of Section 21E of the Securities Exchange Act of 1934. For example,
statements including terms such as "projects," "expects," "believes,"
"anticipates" or "targets" are forward-looking statements. Actual results could
differ materially from those anticipated in such forward-looking statements as a
result of certain factors, including those set forth under "Factors That May
Affect Future Results."
RESULTS OF OPERATIONS
Business Combinations. During the fourth quarter of fiscal 2000, the
Company acquired VirSim, a software product, from Innoveda, Inc., for a purchase
price of approximately $7.0 million in cash. The purchase price of the
transaction was allocated to the acquired assets based on their estimated fair
values as of the date of the acquisition. Amounts allocated to intangible assets
and goodwill are being amortized on a straight-line basis over a three-year
period.
During the third quarter of fiscal 2000, the Company acquired The
Silicon Group, Inc. (TSG), a privately held provider of integrated circuit (IC)
design and intellectual property (IP) integration services, for a purchase price
of $3.0 million, including cash payments of $1.8 million. The purchase price was
allocated to the acquired assets and liabilities based on their estimated fair
values at the time of the acquisition. Amounts allocated to intangible assets
and goodwill are being amortized on a straight-line basis over a four-year
period.
During the first quarter of fiscal 2000, the Company acquired Leda, S.A.
(Leda), a privately held provider of RTL coding-style-checkers, for a purchase
price of $7.7 million, including cash payments of $7.5 million. The purchase
price of the transaction was allocated to the acquired assets and liabilities
based on their estimated fair values as of the date of the acquisition. Amounts
allocated to developed technology, workforce and goodwill are being amortized on
a straight-line basis over a five-year period. Approximately $1.8 million was
allocated to in-process research and development and charged to operations
because the acquired technology had not reached technological feasibility and
had no alternative uses.
Disposition of Viewlogic PCB/Systems Business -- Effect on Comparative
Financial Information. The Company merged with Viewlogic in December 1997 in a
transaction accounted for as a pooling of interests. On October 2, 1998, the
Company sold the printed circuit board and electronics systems business
(PCB/Systems business) of Viewlogic. In the discussion below, financial
information for fiscal 1999 excludes the PCB/Systems business, while financial
information for fiscal 1998 includes the results of the PCB/Systems business.
Therefore, the comparative measures included in the discussion, in particular
with respect to absolute dollar amounts of revenue or expenditure, are not
necessarily valid with respect to the Company's business as it is presently
conducted. A pro forma unaudited consolidated statement of income for 1998,
excluding the results of the PCB/Systems business and certain unusual charges,
was filed with the Securities and Exchange Commission (SEC) on Form 8-K on
January 25, 1999.
Revenue. Revenue consists of fees for licenses and subscriptions of the
Company's software products. The Company's total revenue decreased by 3% in
fiscal 2000 compared to fiscal 1999. The decrease in revenue in fiscal 2000 was
primarily attributable to changes we made to our license model at the beginning
of the fourth quarter of fiscal 2000. Total revenue for the one month transition
period ended October 31,1999 was $23.2 million with product and service revenue
of $4.2 million and $19.0 million, respectively. This is compared to the one
month ended October 31, 1998 with total revenue of $28.2 million with product
and service revenue of $9.9 million and $18.3 million, respectively.
On July 31, 2000, Synopsys introduced Technology Subscription Licenses
(TSLs). TSLs are time-limited rights to use Synopsys software. The terms of
TSLs, and the payments due thereon, may be structured flexibly to meet the needs
of the customer. For creditworthy customers, payments will often extend over the
entire term of the license. With minor exceptions, under TSLs, customers cannot
obtain major new products developed or acquired during the term of their license
without making an additional purchase. TSLs will be structured so that both
product and service revenue will generally be recognized ratably over the term
of the license, or as payments become due. We expect that the average duration
of TSLs will be approximately three years.
Synopsys expects that approximately 75% of its new product orders will
be for TSLs and approximately 25% will be for perpetual licenses, in each case
plus or minus 5%. Synopsys believes that the principal benefits of TSLs will be
that Synopsys will (i) be able to offer customers technology and terms that more
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closely match their needs; (ii) have greater visibility into our earnings
stream; (iii) see improvements in the pricing environment for our products; and
(iv) be able to roll out our new technology in a more planned manner.
The replacement of time-based licenses by subscription licenses will
impact our reported revenue, and reported revenue declined in the fourth quarter
of fiscal 2000, as compared to both the fourth quarter of fiscal 1999 and the
third quarter of fiscal 2000. Under a subscription license, relatively little
revenue is recognized during the quarter the product is delivered, and the rest
goes into deferred revenue to be recognized over the term of the license. Under
the old form of time-based license, generally all license revenue has been
recognized in the quarter the product is delivered, with relatively little going
into deferred revenue. Therefore, an order for subscription licenses will result
in much less current-quarter revenue than an equal-sized order for the old form
of time-based license.
Product revenue decreased by 13% to $442.5 million in fiscal 2000 from
$505.8 million in fiscal 1999 and increased by 17% from $431.0 million in fiscal
1998 compared to fiscal 1999. The decrease in fiscal 2000 is primarily due to
the change in the license model to TSLs, which are recognized ratably over the
term of the license. The increase in fiscal 1999 is primarily due to increased
worldwide licensing and sales of the Company's EDA software products such as
synthesis, verification and system level design software products. Service
revenue increased by 14% to $341.3 million in fiscal 2000 from $300.3 million in
fiscal 1999 and by 5% from $287.0 million in fiscal 1998 compared to fiscal
1999. For each of the years, these increases were primarily attributable to the
renewal of maintenance and support contracts for EDA products and growth in
customer training and consulting services.
Revenue from international operations was $327.0 million, $275.2 million
and $279.8 million, or 42%, 34% and 39% of total revenue in fiscal 2000, 1999
and 1998, respectively. The increase in international revenue as a percentage of
total revenue in fiscal 2000 compared to fiscal 1999 was primarily a result of
relatively greater revenue growth in Japan and Asia Pacific. This revenue
increase for this region is due to the continued economic recovery in the
Pacific Rim and the Company's increased sales focus in this region during fiscal
2000. Revenue from our international operations decreased 31% to $8.7 million
for the one month transition period ended October 31, 1999, compared to $12.5
million for the one month ended October 31, 1998. This decrease is attributed to
reduced customer shipment requests to receive licenses in October 1999.
International revenue represented approximately 37% and 44% of total revenue for
the one-month ended October 31, 1999 and 1998, respectively.
Revenue -- Product Groups. For management reporting purposes, the
Company's software products have been organized into four distinct product
groups -- IC Implementation (composed of two product categories, DC Family and
Physical Synthesis), Verification and Test, IP and Systems Design, Transistor
Level Design (TLD), and a services group -- Synopsys(R) Professional Services.
The following table summarizes the performance of the various groups as a
percentage of total company revenue:
YEAR ENDED
OCTOBER 31, YEARS ENDED SEPTEMBER 30,
----------- -------------------------
(in thousands) 2000 1999 1998
- -------------- ----------- ------ -------
Revenue:
IC Implementation
DC Family 35% 39% 36%
Physical Synthesis 4% 1% --
Verification and Test 30% 26% 21%
IP and System Level Design 14% 14% 22%(1)
Transistor Level Design 7% 12% 11%
Professional Services 10% 8% 10%
--- --- ---
Total Company 100% 100% 100%
=== === ===
(1) Includes revenue from Viewlogic's systems & PCB design business. The
segment was sold to a management-led buy-out group during fiscal 1998.
IC Implementation. During fiscal 2000, the Company introduced Physical
Compiler, a product that unifies synthesis, placement and global routing.
Included in the Physical Synthesis family are Chip Architect, the Company's chip
floor-planning product, Flex Route, the Company's high-level router and the
Company's detailed routing technology. This product family contributed revenue
of $32.6 million during fiscal 2000. The Company expects continued increases in
the revenue contribution from the Physical Synthesis family in future years. The
decline in revenue contribution percentage of the DC family from fiscal 1999 to
fiscal 2000 reflects the maturation of the market for Design Compiler and the
beginning of what we believe is a transition from the DC family to the newer
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generation of products. The Company expects that revenue and orders from the DC
family will remain approximately flat from fiscal 2000 to fiscal 2001, and then
will begin to decline. Future revenue growth in the IC Implementation product
group is anticipated to come from the Physical Synthesis product family.
Verification and Test. Verification and Test includes the Company's
simulation, timing analysis, formal verification and test products. The increase
in percentage of total company revenue from fiscal 1999 to fiscal 2000 is due to
greater demand for verification products from our customers. The Company expects
demand for verification products to continue to increase as both systems and
semiconductor companies experience a crisis in verification.
Intellectual Property and System Level Design (IP&SG). The Company's
Intellectual Property and System Level Design products include DesignWare,
models, system design products and cell libraries (recently sold to Artisan
Components -- see Note 10, Subsequent Events, of Notes to Synopsys' Consolidated
Financial Statements). Revenue contribution has remained relatively constant
over the last three fiscal periods, even with the Viewlogic's Systems & PCB
design business segment sale. Revenue growth within the IP&SG group has come
primarily from DesignWare, as this product has grown significantly faster other
products with in the group.
Transistor Level Design. The Company's transistor level design products
include the products acquired though the acquisition of Epic Design Technology,
which was completed in fiscal 1997. These tools are used in the transistor-level
simulation and analysis. The decline in revenue contribution from 12% in fiscal
1999 to 7% in fiscal 2000 was due to the lack of significant large orders during
fiscal 2000 and the effects of competition. This decline also impacted overall
Company performance in fiscal 2000. The Company believes the technology embedded
in these tools will have significant value to our customers as these customers
migrate to smaller geometries in their chip designs.
Professional Services. The Company's Professional Services group
includes consulting and training activities as well as the Company's new
Internet Design Service Business. The Professional Services group provides a
comprehensive portfolio of consulting services covering all critical phases of
the system-on-a-chip development process, as well as systems development in
wireless and broadband applications. The increase in the total Company revenue
contribution for this services group from 8% in fiscal 1999 to 10% in fiscal
2000 is due largely to the increased demand for the Company's turnkey design and
wireless and broadband consulting services. The Company anticipates continued
growth in fiscal 2001.
Cost of Revenue. Cost of product revenue includes personnel and related
costs, production costs, product packaging, documentation, amortization of
capitalized software development costs and purchased technology, and costs of
the components of the Company's hardware system products. The cost of internally
developed capitalized software is amortized based on the greater of the ratio of
current product revenue to the total of current and anticipated product revenue
or the straight-line method over the software's estimated economic life of
approximately two years. Cost of product revenue was 10% of total product
revenue for fiscal 2000, as compared to 8% for fiscal 1999. The increase in cost
of product revenue is due primarily to the change in the license strategy
introduced in Q4 of fiscal 2000. The Company's product costs are relatively
fixed and do not fluctuate significantly with changes in revenue or changes in
revenue recognition methods. Cost of product revenue for fiscal 1998 was 8% of
total product revenue. Cost of service revenue includes personnel and the
related costs associated with providing training and consulting services. Cost
of service revenue as a percentage of total service revenue was 24% in fiscal
2000, 23% in fiscal 1999 and 20% in 1998. The increases in cost of service
revenue over the last two fiscal periods results from the continued investment
in the Company's infrastructure required to expand its consulting and training
businesses. For the one-month transition period ended October 31, 1999, cost of
revenue, as a percentage of total revenue was 32% compared to 31% for the one
month ended October 31, 1998. The increase in cost of revenue resulted primarily
from increased royalties and personnel costs relating to maintenance and
support. The Company expects that cost of revenue in fiscal 2001 will remain
flat or increase slightly. In addition, fiscal 2001 will include an additional
week of operations due to the method by which we determine our fiscal year.
Research and Development. Research and development expenses increased by
13% to $189.3 million in fiscal 2000, from $167.1 million in fiscal 1999, and by
7% in fiscal 1999 compared to $156.7 million in fiscal 1998, net of capitalized
software development costs. Research and development expenses represented 24%,
21% and 22% of total revenue in fiscal 2000, 1999 and 1998, respectively. The
increase in absolute dollars reflects the Company's ongoing research and
development. A significant portion of the increase for each fiscal year was due
to the addition of personnel and personnel related costs, partly through
acquisitions, for enhancement of existing applications and development of new
products. Also, fiscal 1998 included an additional week of operations, which was
partially offset by synergies realized from the integration of Viewlogic into
Synopsys' operations. Research and development expenses for the one-month
transition period ended October 31, 1999 were $17.2 million as compared to $14.9
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million for the one-month ended October 31, 1998. This increase can be
attributed to increases in personnel and personnel related costs. The Company
anticipates that it will continue to commit substantial resources to research
and development in the future, provided that it is able to continue to hire and
retain a sufficient number of qualified personnel. If the Company believes that
it is unable to enter a particular market in a timely manner, it may license
technology from other businesses or acquire other businesses as an alternative
to internal research and development. Fiscal 2001 will include an additional
week of operations due to the method by which we determine our fiscal year.
Sales and Marketing. Sales and marketing expenses increased by 20% to
$288.8 million in fiscal 2000 from $241.6 million in fiscal 1999 and decreased
by 2% from $245.4 million in fiscal 1998 compared to fiscal 1999. Sales and
marketing expenses represented 37%, 30% and 34% of total revenue in fiscal 2000,
1999 and 1998, respectively. Total expenses increased in absolute dollars and as
a percentage of revenue in fiscal 2000 primarily as a result of increases in
personnel related costs. Total expenses decreased in absolute dollars and as a
percentage of revenue in fiscal 1999 primarily as a result of the divestiture of
the PCB/Systems business, as well as savings resulting from ongoing integration
of Viewlogic's other operations into the Company as a whole. The fiscal 1998
increase over fiscal 1999 primarily resulted from the additional week of
operations. Sales and marketing expenses for the one-month transition period
ended October 31, 1999 were $19.0 million as compared to $16.9 million for the
one-month ended October 31, 1998. This increase primarily related to the higher
costs associated with the 1999 annual business planning events. Fiscal 2001 will
include an additional week of operations due to the method by which we determine
our fiscal year.
General and Administrative. General and administrative expenses
increased to $59.2 million in fiscal 2000 compared to $47.1 million in fiscal
1999. General and administrative expense decreased slightly from $47.2 million
in fiscal 1998 compared to fiscal 1999. As a percentage of total revenue,
general and administrative expenses were 8%, 6% and 7% in fiscal 2000, 1999 and
1998, respectively. In fiscal 2000, the increase in absolute dollars and
percentage of revenue was primarily due to increases in bad debt expense,
personnel costs, facility expenditures and patent and proxy services. General
and administrative expenses for the one-month transition period ended October
31, 1999 were $5.7 million as compared to $4.9 million for the one-month ended
October 31, 1998. This increase was primarily a result of higher professional
service fees. Fiscal 2001 will include an additional week of operations due to
the method by which we determine our fiscal year.
Operating Expense Targets -- Fiscal 2001. For Fiscal 2001, our target
for overall operating expense growth over fiscal 2000, before the amortization
of intangible assets, is 2.5% to 3.5%.
Amortization of Intangible Assets. Amortization of intangible assets
represents the excess of the aggregate purchase price over the fair value of the
tangible and identifiable intangible assets acquired by the Company. Under the
Company's accounting policies, intangible assets as of October 31, 2000,
including goodwill, are being amortized over the estimated useful life of three
to five-year periods. The Company assesses the recoverability of goodwill by
determining whether the amortized asset over its useful life may be recovered
through estimated future undiscounted cash flows. Amortization of intangible
assets charged to operations in fiscal 2000 was $15.1 million as compared to
$7.9 million for fiscal 1999. Amortization of intangible assets charged to
operations for the one-month ended October 31, 1999 was $1.2 million.
Amortization of intangible assets for the one-month ended October 31, 1998 was
not material.
Merger-Related and Other Costs. As a result of various business
combinations accounted for as pooling of interests during fiscal 1998, the
Company incurred merger-related and other costs of $51.0 million. These expenses
related to transaction costs, employee termination and transition costs, legal
costs, write-off of equipment and other assets, and redundant facility and other
costs. During fiscal 1999 and fiscal 2000, the Company did not incur any
merger-related or other costs related to business combinations accounted for as
a pooling of interests.
In-Process Research and Development. The following paragraphs contain
forward-looking statements within the meaning of Section 21E of the Securities
Exchange Act of 1934, including statements and assumptions regarding percentage
of completion, expected product release dates, dates for which we expect to
begin generating benefits from projects, expected product capabilities and
product life cycles, costs and efforts to complete projects, growth
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rates, royalty rates and projected revenue and expense information used by us to
calculate discounted cash flows and discounts rates. These forward-looking
statements involve risks and uncertainties, and the cautionary statements set
forth below and in "Factors that May Affect Future Results" identify important
factors that could cause actual results to differ materially from those
predicted in any such forward-looking statement.
Purchased in-process research and development (IPRD) of $1.7 million and
$21.2 million in fiscal 2000 and 1999 respectively, represent the write-off of
in-process technologies associated with our acquisitions of Leda in fiscal 2000
and Gambit Automated Design, Inc. (Gambit), Stanza Systems, Inc. (Stanza),
Smartech, the rights to CoverMeter, a software product owned by Advanced
Technology Center, and Apteq Design Systems, Inc. (Apteq), in fiscal 1999. At
the date of each acquisition the projects associated with the IPRD efforts had
not yet reached technological feasibility and the research and development in
process had no alternative future uses. Accordingly, these amounts were expensed
on the respective acquisition dates of each of the Acquired Companies. (Also see
Note 3, Business Combinations, of Notes to Synopsys' Consolidated Financial
Statements.)
Valuation of IPRD. We calculated amounts allocated to IPRD using
established valuation techniques in the high technology industry and expensed
such amounts in the quarter that each acquisition was consummated because
technological feasibility had not been achieved and no alternative future uses
had been established. This approach gave consideration to relevant market sizes
and growth factors, expected industry trends, the anticipated nature and timing
of new product introductions by us and our competitors, individual product sales
cycles, and the estimated life of each products' underlying technology.
The fair value of the in-process technology was based on a discounted
cash flow model, similar to the traditional "Income Approach," which discounts
expected future cash flows to present value, net of tax. In discounting the
estimated cash flows, the discount rates used in the present value calculations
were typically derived from a weighted-average cost of capital analysis,
adjusted upward to reflect additional risks inherent in the development life
cycle, the risks associated with achieving such projected cash flows upon
successful completion of the acquired projects and the risks and uncertainties
in incorporating the acquired technology into the Company's development
projects.
Other Income, Net. Other income, net was $40.8 million, $37.0 million
and $26.0 million, or 5%, 5% and 4% of total revenue in fiscal 2000, 1999 and
1998, respectively. Other income, net increased in absolute dollars each fiscal
year primarily due to higher interest income from higher invested cash balances
in fiscal 1999 and from a higher mix of taxable to tax-exempt investments in
fiscal 2000. In addition, in fiscal 2000, 1999 and 1998 other income, net
increased due to gains realized on sales of equity investments. Other income,
net for the one-month transition period ended October 31, 1999 was $1.7 million
as compared to $1.1 million for the one-month ended October 31, 1998.
Interest Rate Risk. The Company's exposure to market risk for changes in
interest rates relate primarily to its investment portfolio. The Company does
not use derivative financial instruments for speculative or trading purposes
with respect to its cash and short-term investments. The Company places its
investments in a mix of tax-exempt and taxable instruments that meet high credit
quality standards, as specified in the Company's investment policy. The policy
also limits the amount of credit exposure to any one issue, issuer and type of
instrument. The Company does not anticipate any material loss with respect to
its investment portfolio.
The following table presents the carrying value and related
weighted-average after tax interest rates for the Company's investment portfolio
at October 31, 2000. The carrying value approximates fair value at that date. In
accordance with the Company's investment policy, all investments mature in
fifteen months or less.
Principal (Notional) Amounts in U.S. Dollars:
(in thousands, except interest rates)
Weighted
Avg.
Carrying After Tax
Amount Interest Rate
-------- -------------
Cash equivalents - fixed rate $ 9,993 4.40%
Short-term investments - fixed rate 282,519 4.51%
--------
Total investment securities 292,512 4.50%
Money market funds -- variable rate 59,377 4.40%
--------
Total interest bearing instruments $351,889 4.49%
========
(See Note 4, Financial Instruments, in accompanying notes to consolidated
financial statements for additional information on investment maturity dates,
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long-term debt and equity price risk related to the Company's long-term
investments.)
Foreign Currency Risk. At the present time, the Company does not
generally hedge anticipated foreign currency cash flows but hedges only those
currency exposures associated with certain assets and liabilities denominated in
nonfunctional currencies. Hedging activities undertaken by the Company are
intended to offset the impact of currency fluctuations on these balances. The
success of this activity depends upon estimates of intercompany balances
denominated in various currencies, primarily the Japanese yen and the euro. The
Company had contracts for the sale and purchase of foreign currencies with a
notional value expressed in U.S. dollars of $47.5 million. Looking forward, the
Company does not anticipate any material adverse effect on its consolidated
financial position, results of operations, or cash flows resulting from the use
of these instruments. There can be no assurance in the future that these hedging
transactions will be effective.
The following table provides information about the Company's foreign
exchange forward contracts at October 31, 2000. Due to the short-term nature of
these contracts, the amount in U.S. dollars approximates the fair value of the
contract at October 31, 2000. These forward contracts mature in approximately
thirty days.
Short-Term Forward Contracts to Sell and Buy Foreign Currencies in U.S. Dollars
Related to Intercompany Balances:
(in thousands)
Contract
Amount Rate
-------- --------
Forward Contract Values:
Japanese Yen $ 25,471 107.27
Euro $ 22,050 0.83733
The unrealized gains/losses on the outstanding forward contracts at
October 31, 2000 were immaterial to the Company's consolidated financial
statements. The realized gain/loss on these contracts as they matured were not
material to the Company's consolidated financial position, results of
operations, or cash flows for the periods presented.
Derivative Financial Instruments. Apart from its foreign currency
hedging and forward sales of certain equity investments, the Company does not
use derivative financial instruments. In particular, the Company does not use
derivative financial instruments for speculative or trading purposes.
Extraordinary Items. During fiscal 2000 and 1999, the Company incurred
no extraordinary gains or losses. During the first quarter of fiscal 1998, the
Company recorded an extraordinary gain on extinguishment of debt of $1.9
million, net of income tax expense of $1.0 million, related to the cancellation
of certain interest bearing notes issued by the Company to International
Business Machines Corporation (IBM).
During the fourth quarter of fiscal 1998, Synopsys completed the partial
spin-off of Viewlogic Systems, Inc. (VSI), a company that owns the printed
circuit board (PCB/Systems business) of Viewlogic. Synopsys' merger with
Viewlogic in December 1997 was accounted for as a pooling of interests. The
spin-off was accounted for as an extraordinary item, as provided by paragraph 60
of Accounting Principles Board Opinion No. 16 (APB 16), and Synopsys recorded an
extraordinary gain, net of income tax expense, of $26.5 million in fiscal 1998
in respect to the spin-off. Synopsys retained common stock equal to 14.9% of the
fully diluted equity in VSI.
The Company concluded that the disposition of VSI was consistent with
its treatment of the Synopsys-Viewlogic merger as a pooling of interests. A
condition of the pooling-of-interests treatment is that at the time of the
merger, management did not plan to dispose of any significant part of the assets
of the merged entity. The Company concluded that this condition was met because,
on the date of the Synopsys-Viewlogic merger, the Company did not plan to
dispose of the PCB/Systems business. The Company believed that there would be
synergies between the Company's "high-level" integrated circuit design products
and VSI's PCB design products. The ultimate decision to spin-off VSI was based
on changes in circumstances following the Synopsys-Viewlogic merger.
During the months following the merger, the Company came to realize that
certain of its assumptions and expectations regarding the operation of the
PCB/Systems business as part of Synopsys were not being fulfilled. The Company's
initial intent to retain VSI altered due to changes in circumstances as follows:
- A number of engineers working in the PCB/Systems business were
hired by competitors, and management became concerned that it
would lose more if the business remained part of Synopsys.
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- Certain synergies anticipated from operation of the PCB/Systems
business as part of Synopsys did not materialize.
- The revenues of the PCB/Systems business grew more slowly than
those of Synopsys' other businesses. Management concluded that
the reduction in the Company's overall growth rate caused by the
PCB/Systems business was contributing to a market discounting of
the Company's stock value.
- Managers of the PCB/Systems business concluded that the business
could grow faster if it was a stand-alone entity, which would
allow them to attract and retain key employees.
Accordingly, Synopsys has not changed its accounting for the Viewlogic
merger and has reported the gain on the VSI disposition as an extraordinary
item.
EFFECT OF NEW ACCOUNTING STANDARDS
In December 1998, the AICPA issued Statement of Position (SOP) 98-9,
Modification of SOP 97-2, Software Revenue Recognition, With Respect to Certain
Transactions, which amends SOP 97-2 and supercedes SOP 98-4. The Company adopted
SOP 98-9 during fiscal 2000. The adoption of the statement did not have a
material impact on the Company's consolidated financial position or results of
operations, as the Company modified certain business practices. See Note 1 to
Notes to Synopsys' Consolidated Financial Statements.
In fiscal 2000, the Emerging Issues Task Force (EITF) published their
consensus on EITF Issue No. 00-2, Accounting for Web Site Development Costs,
which requires that costs incurred during the development of web site
applications and infrastructure, including developing software to operate the
web site, and including graphics that affect the "look and feel" of the web page
and all costs relating to software used to operate a web site should be
accounted for under Statement of Position 98-1, Accounting for the Costs of
Computer Software Developed or Obtained for Internal Use, (SOP 98-1). The
Company adopted EITF No. 00-2 in fiscal 2000. The adoption did not have a
material effect on our consolidated financial position or results of operations.
In fiscal 2000, the EITF published their consensus on Issue No. 00-3,
Application of AICPA Statement of Position 97-2, Software Revenue Recognition,
to Arrangements That Include the Right to Use Software Stored on Another
Entity's Hardware. The Issue states that a software element covered by SOP 97-2
is only present in a hosting arrangement if the customer has the contractual
right to take possession of the software at any time during the hosting period
without significant penalty and it is feasible for the customer to either run
the software on its own hardware or contract with another party unrelated to the
vendor to host the software. The Company recently introduced a software hosting
service. Synopsys hosting services agreements now in place do not grant
customers the right to take possession of hosted software without an additional
charge.
In fiscal 2000, the Financial Accounting Standards Board (FASB) issued
Interpretation No. 44, Accounting for Certain Transactions involving Stock
Compensation, an interpretation of APB Opinion No. 25. This Interpretation
clarifies the application of Opinion 25 for certain issues including: (a) the
definition of employee for purposes of applying Opinion 25, (b) the criteria for
determining whether a plan qualifies as a noncompensatory plan, (c) the
accounting consequence of various modifications to the terms of a previously
fixed stock option or award, and (d) the accounting for an exchange of stock
option awards in a business combination. The Company adopted Interpretation 44
in fiscal 2000 and the adoption did not have a material effect on our
consolidated financial position or results of operations.
In June 1999, the FASB issued Statement of Financial Accounting
Standards (SFAS) Nos. 137 and 138, Accounting for Derivative Instruments and
Hedging Activities, which amends the effective date of SFAS No. 133, Accounting
for Derivative Instruments and Hedging Activities. SFAS No. 133 establishes
accounting and reporting standards for derivative financial instruments and
hedging activities and requires the Company to recognize all derivatives as
either assets or liabilities on the balance sheet and measure them at fair
value. Gains and losses resulting from changes in fair value would be accounted
for based on the use of the derivative and whether it is designated and
qualifies for hedge accounting. The Company will adopt SFAS No. 133 for the
fiscal year beginning November 1, 2000. The Company does not expect to have a
transition adjustment related to the adoption of SFAS 133.
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During fiscal 2000, the Securities and Exchange Commission issued Staff
Accounting Bulletin No. 101 ("SAB 101"), Revenue Recognition in Financial
Statements. The objective of SAB 101 is to provide further guidance on revenue
recognition issues in the absence of authoritative literature addressing a
specific arrangement or a specific industry. The Company is required to adopt
the guidance in SAB 101 no later than the fourth quarter of its fiscal year
2001. Adoption of this guidance is not expected to have a material impact on the
Company's financial position or results of operations.
LIQUIDITY AND CAPITAL RESOURCES
Cash, cash equivalents and short-term investments were $435.6 million at
October 31, 2000, a decrease of $273.8 million or 39% from October 31, 1999. The
decrease is primarily a result of cash outflow for financing and investing
activities, mainly the repurchase of common stock of $397.5 million, capital
expenditures of $68.5 million, cash paid for acquisitions of $14.5 million, and
cash paid on debt obligations of $14.3 million. These outflows were partially
offset by cash generated by operations of $151.1 million and through investing
and financing activities, mainly the exercise of stock options and sale of stock
through the employee stock purchase plan of $59.5 million, and proceeds from
sale of long-term investments of $24.3 million.
Accounts receivable increased 12% during fiscal 2000, while sales
declined by 3% to $783.8 million in fiscal 2000 from $806.1 million in fiscal
1999. Days sales outstanding in receivables increased to 99 days as of October
31, 2000 from 61 days at September 30, 1999, largely as a result of decreased
revenue in the fourth quarter of fiscal 2000 as compared to the same period in
fiscal 1999. The decrease in revenues during the fourth quarter of fiscal 2000
was the result of a change in the Company's license and pricing strategy. As of
October 31, 2000, the remaining balance of the Company's accounts receivable
sold to a financial institution was $5.3 million.
The Company's management believes that its current cash, cash
equivalents, short-term investments, and cash generated from operations will
satisfy its expected working capital and capital expenditure requirements for at
least the next twelve months.
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FACTORS THAT MAY AFFECT FUTURE RESULTS
Our Revenue and Earnings May Fluctuate. Many factors affect our revenue
and earnings, which makes it difficult to achieve predictable revenue and
earnings growth. Among these factors are customer product and service demand,
product license terms, and the timing of revenue recognition on products and
services sold. The following specific factors could affect our revenues and
earnings in a particular quarter or over several quarterly or annual periods:
- - Our orders have been, and are expected to continue to be, seasonal.
Historically, our first fiscal quarter has been our weakest.
- - Our products are complex, and before buying them customers spend a great
deal of time reviewing and testing them. Our customers' evaluation and
purchase cycles do not necessarily match our quarterly periods. Like
many companies in the software industry, in the past we have received a
disproportionate volume of orders in the last week of a quarter. In
addition, a large proportion of our business is attributable to our
largest customers. As a result, if any order, and especially a large
order, is delayed beyond the end of a fiscal period, our orders and
revenue for that period could be below our plan.
- - Accounting rules determine when revenue is recognized on our product and
service contracts, and therefore impact how much revenue we will report
in any given fiscal period. The authoritative literature under which the
Company recognizes revenue has been, and is expected to continue to be,
the subject of much interpretative guidance. In general, following the
change to our license model in the fourth quarter of fiscal 2000, most
orders for our products and services yield revenue over multiple
quarters (extending beyond the current fiscal year) or upon completion
of performance rather than at the time the contract is executed. The
specific terms agreed to with a customer may have the effect of
requiring deferral or acceleration of revenue in whole or in part.
Therefore, for any given fiscal period it is possible for us to fall
short in our revenue and/or earnings plan even while orders and backlog
remain on plan or, conversely, to meet our revenue and/or earnings plan
because of backlog and deferred revenue while orders are under plan.
- - In fiscal 2000, we modified the license and pricing structure for our
software products twice. We believe that the changes we made in August
2000 (the adoption of Technology Subscription Licenses) are producing
benefits for both Synopsys and our customers, but it remains possible
that customer reaction will be unfavorable or; that the transition to
the new structure will be disruptive to business, in either case
resulting in the deferral or loss of sales, or that our planned mix of
license types will not be achieved.
Our Industry is Highly Competitive. The EDA industry is highly
competitive. We compete against other EDA vendors, and with customers'
internally developed design tools and internal design capabilities, for a share
of the overall EDA budgets of our potential customers. In general, competition
is based on product quality and features, post-sale support, price and, as
discussed below, the ability to offer a complete design flow. Our competitors
include companies that offer a broad range of products and services, such as
Cadence, Mentor and Avant!, as well as companies, including numerous start-up
companies, that offer products focused on a discrete phase of the integrated
circuit design process. In certain situations, Synopsys' competitors have been
offering aggressive discounts on certain of their products, in particular
simulation and synthesis products. As a result, average prices for these
products may fall. In order to compete successfully, we must continue to enhance
our products and bring to market new products that address the needs of our
customers. We also will have to expand our consulting services business. The
failure to enhance existing products, develop and/or acquire new products or
expand our ability to offer consulting services could have a material adverse
effect on our business, financial condition and results of operations.
Technology advances and customer requirements continue to fuel a change
in the nature of competition among EDA vendors. Increasingly, EDA companies
compete on the basis of "design flows" involving integrated logic and physical
design products (referred to as "physical synthesis" products) rather than on
the basis of individual "point" tools performing a discrete phase of the design
process. The need to offer physical synthesis products will become increasingly
important, as ICs grow more complex. Our main physical synthesis product was
fully released in June 2000, and has been well received by customers, but we
still do not offer customers a complete design flow. We are working on
completing our design flow, although there is no guarantee that we will be able
to offer a competitive flow to customers. The market for physical design tools
is dominated by Cadence and Avant!, both of which offer products linking logic
and physical design. If we are unsuccessful in developing a complete design flow
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on a timely long-term debt basis or in convincing customers to adopt our
integrated logical and physical design products and methodology, our competitive
position could be significantly weakened.
Our Revenue Growth Depends on New and Non-Synthesis Products.
Historically, much of our growth has been attributable to the strength of our
logic synthesis products. These products accounted for 35% of revenue in fiscal
2000. We believe that orders and revenues for our flagship logic synthesis
product, Design Compiler, peaked in fiscal 2000. Therefo