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UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549

FORM 10-K

Commission File Number 0-19807

SYNOPSYS, INC.
(Exact name of registrant as specified in its charter)

700 East Middlefield Road, Mountain View, California 94043
(Address of principal executive offices, including zip code)

(650) 584-5000
(Registrant's telephone number, including area code)

Securities Registered Pursuant to Section 12(b) of the Act: None

Securities Registered Pursuant to Section 12(g) of the Act:

Common Stock, $0.01 par value
(Title of Class)

Preferred Share Purchase Rights
(Title of Class)

        Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes ý    No o

        Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. ý

        Indicate by check mark whether the Registrant is an accelerated filer (as defined in Rule 12b-2 of the Act). Yes ý    No o

        The aggregate market value of the voting and non-voting common equity held by non-affiliates computed by reference to the price at which the common equity was last sold as of the last business day of the Registrant's most recently completed second fiscal quarter was approximately $2,971,050,000. Aggregate market value excludes an aggregate of 43,963,564 shares of common stock held by officers and directors and by each person known by the Registrant to own 5% or more of the outstanding common stock on such date. Exclusion of shares held by any of these persons should not be construed to indicate that such person possesses the power, direct or indirect, to direct or cause the direction of the management or policies of the Registrant, or that such person is controlled by or under common control with the Registrant.

        On January 1, 2005, 146,017,235 shares of the Registrant's Common Stock, $0.01 par value, were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

        None.

SYNOPSYS, INC.
ANNUAL REPORT ON FORM 10-K
Year ended October 31, 2004

TABLE OF CONTENTS

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PART I

        This Annual Report on Form 10-K, particularly in Item 1. "Business" and Item 7. "Management's Discussion and Analysis of Financial Condition and Results of Operations," includes forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 (the Securities Act) and Section 21E of the Securities Exchange Act of 1934 (the Exchange Act). These statements include, but are not limited to, statements concerning: our business, product and platform strategies expectations regarding previous and future acquisitions; completion of development of our unfinished products or further development or integration of our existing products; expectations regarding bookings, revenue, earnings, changes in operating expenses, cash flows, gross margin and operating margin in fiscal 2005; continuation of current industry trends towards vendor consolidation; expectations regarding our license mix; expectations regarding future maintenance revenue; expectations regarding customer interest in more highly integrated tools and design flows; expectations of the success of our intellectual property and design for manufacturing initiatives; expectations regarding changes in our upfront and time-based revenue in fiscal 2005; expectations regarding revenue seasonality; and our expectations of our future liquidity requirements. Our actual results could differ materially from those projected in the forward-looking statements as a result of a number of factors, risks and uncertainties discussed in this Form 10-K, especially under the caption "Factors that May Affect Future Results," in Item 7 in this Form 10-K. The words "may," "will," "could," "would," "anticipate," "expect," "intend," "believe," "continue," or the negatives of these terms, or other comparable terminology and similar expressions identify these forward- looking statements. The information included herein is given as of the filing date of this Form 10-K with the Securities and Exchange Commission (SEC) and future events or circumstances could differ significantly from these forward-looking statements. Furthermore, we assume no obligation, and do not intend, to update these forward-looking statements except as required by law.

Item 1. Business

Introduction

        Synopsys, Inc. (Synopsys) is a world leader in electronic design automation (EDA) software for semiconductor design. We deliver technology-leading semiconductor design and verification software platforms and integrated circuit (IC) manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). We also provide intellectual property (IP) and design services to simplify the design process, and accelerate time-to-market for our customers.

        We incorporated in 1986 in North Carolina and reincorporated in Delaware in 1987. Our headquarters are located at 700 East Middlefield Road, Mountain View, California 94043 and our telephone number is (650) 584-5000. We have more than 60 offices throughout North America, Europe, Japan and Asia.

        Our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, Proxy Statements relating to our annual meetings of stockholders, Current Reports on Form 8-K and amendments to these reports and filings made by our executive officers and directors are available on our Internet website (www.synopsys.com). We post these reports to our website as soon as practicable after we file them with the SEC. The contents of our website are not part of this Form 10-K.

The Role of EDA in the Electronics Industry

        Technology advances in the semiconductor industry have steadily increased the feature density, speed, power efficiency and functional capacity of semiconductors (also referred to as integrated circuits, ICs or chips).

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Since the early 1960s, steadily decreasing feature widths (the widths of the wires imprinted on the chip that form the transistors) and other developments have enabled IC manufacturers to follow "Moore's law," approximately doubling every two years the number of transistors that can be placed on a chip. As a result, state-of-the-art ICs now hold over one hundred million transistors and have feature widths of 90 nanometers (billionths of a meter), going to 65 nanometers and below.



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Microprocessors operating at more than 4 gigahertz, a speed unheard of only a few years ago, are readily available today.



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Chips have become more power efficient to address demand for smaller and more powerful handheld devices such as cell phones, digital cameras, music players and personal digital assistants.



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Increasingly, single SoCs can handle functions formerly performed by multiple ICs attached to a printed circuit board.

        Combined, these advances in semiconductor technology have driven development of lower cost, higher performance computers, wireless communications networks, hand held devices, Internet routers and a wealth of other electronic devices. Each advance, however, has introduced new challenges for all participants in semiconductor production, from designers and manufacturers to equipment manufacturers and EDA software suppliers, such as Synopsys.

The IC Design Process

        EDA software is central to the IC design process, enabling designers to design complex semiconductors by using a high-level, abstract description of the function of the chip. EDA software is used to automatically translate this description into successively more detailed forms, and to verify at each stage in the design process that the chip's design is sound and that the chip when manufactured will function as originally intended.

        In simplified form, the IC design process consists of system design, register transfer level design, logic design, functional verification, physical design and physical verification.

        System Design.    In system design, the designer describes the chip's desired functions in very basic terms using a specialized high-level computer language, typically C++ or System C. This phase yields a relatively high-level behavioral model of the chip.

        Register Transfer Level (RTL) Design.    RTL design is the process of capturing the intended design functionality created at the system level using a specialized high-level computer language, typically Verilog or VHDL. This is the stage where the functionality of the final design is captured in enough detail to begin simulation and verification and determine that the final product will function as expected in the verification phase.

        Logic Design.    Logic design, or "synthesis," programs convert the RTL code into a logical diagram of the chip, and produce a data file known as a net list describing the various groups of transistors, or gates, to be built on the chip. Related programs insert the additional circuitry into the design that will be needed to test the chip after manufacture. In a growing number of designs, designers are increasingly performing "design planning" in which the designer determines the location of the major functional "blocks" on the SoC prior to logic synthesis.

        Functional Verification.    At the RTL and gate level of IC design, the designer uses functional verification tools such as RTL simulators and testbench automation and other verification tools to simulate large sets of inputs that a given IC design might confront in a real-life operation. By running these extensive tests, the designer can verify that the design will function as intended.

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        Physical Design.    In the physical design stage, the designer plans the physical location of all of the transistors and each of the wires connecting them with "place and route" products. The designer first determines the location on the chip die for each block of the chip, as well as the location for each transistor within each block, a process known as "placement." In many designs, placement is performed in conjunction with logic synthesis, a process known as "physical synthesis." After placement the designer adds the connections between the transistors, a process known as "routing." The output of place and route programs is one or more data files that can be read by physical verification or mask data preparation programs.

        Physical Verification.    Before sending the chip design files to a manufacturer for fabrication, the designer must perform a series of further verification steps, checking to make sure that the final design complies with the specific requirements of the fabrication facility that will manufacture the chip. The designer may need to add features to the design to ensure that the chip can be manufactured successfully. The completion of this final phase is called "tapeout."

        In actual chip design, each of these steps has a number of additional elements, and designers often undertake the various design and verification steps in a different order than described above, and repeat one or more steps (particularly functional and physical verification) multiple times. Further, several of the steps, especially logic design and physical design, are becoming more integrated with each other. If at any stage of the process the designer determines the chip design will not perform as intended, the designer must go back one or more steps and correct the problem, then continue through subsequent steps. Recreating a chip's logic design, performing simulation over again, and repeating other steps all take time. Each such iteration adds significant costs and makes it more difficult for the designer to meet time-to-market goals.

Current Issues Facing IC Designers

        As chip technology continues to advance, our customers are seeking to maximize the quality of results of their IC design efforts, while minimizing the costs of achieving these results and shortening the time needed to launch the manufactured IC, as follows:

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Quality of Results. Customers are concerned about differentiating their chips from their competitors' in a number of areas, including size or area, speed, functionality, power consumption and performance. The designer must balance each issue against the others, making key tradeoff decisions—often through multiple iterations—to reach a final design. As chips become more complex and manufacturing geometries shrink, this balancing of factors becomes disproportionately more difficult, and requires designers to successfully address technical issues, including:



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Timing closure: achieving consistency between the speed of the chip at the logic design phase and the speed of the chip at the physical design phase;



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Signal integrity: ensuring chip performance is not affected by unintended electrical effects, like cross-talk and other forms of interference, that occur as the wires on a chip get more narrow and closer together;



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Power management: reducing the chip's power consumption, an important objective for chips to be used in battery-operated devices, particularly in the case of laptop computers and cell phones where both longer battery life and lower power drain in standby mode is critical;



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Design for test: embedding circuits in the design that allow the chip, once manufactured, to be tested rapidly and at a reasonable cost;



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Verification: verifying that the chip will perform as intended, which has become the single most time-consuming and resource intensive aspect of overall design;

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Manufacturability: faithfully translating the design produced by EDA tools into a manufacturable pattern of wires and transistors on the chip has become significantly more difficult as a result of decreasing feature widths and increasing feature density; and



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Yield: ensuring that an acceptable number of good chips per wafer can be manufactured successfully.



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Cost of Results. Customers are continually seeking to constrain their costs, including costs of design, masks, equipment, facilities and support, all of which typically increase as chips become more complex. The higher the cost, the higher the expected volume of chips the customer must sell to make a given chip project profitable. Faced with increasing costs, our customers continue to focus intensely on controlling their research and development and manufacturing costs, including their EDA software costs and maximizing their yield in manufacture. As a result, many of our customers have begun consolidating suppliers to improve their purchasing terms and, more importantly, to gain the benefits of better integrated products.



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Time to Results. Finally, customers are seeking to improve the predictability of their production schedule. Economic pressures, competition and continuing innovation continue to shorten the life cycle of electronic products. Accordingly, time-to-market is critical to a product's commercial success. The design time for a product's IC components is a major determining factor of that product's time-to-market. Accordingly, our customers require EDA products that can address the challenges described above while reducing overall design time.

Strategy

        We provide products and services that help our customers design leading-edge ICs while maximizing achievement of their quality of results, cost of results and time to results goals.

        Historically, customers have purchased individual "point tools" to complete one or more tasks or sets of tasks in the design process, dealing internally with moving from one design environment or data set to the next, while integrating various products—or even developing design tools—themselves where necessary. However, with the increasing complexity of IC design, cost pressures and ever smaller market windows, customers require broader solutions with greater performance from fewer vendors at lower costs.

        To meet this need, we have combined our individual products—many of which lead their respective categories—into platforms, or collections of products that are integrated through the use of common interfaces, data sets and other technologies, to deliver a comprehensive, faster and more reliable design flow. In fiscal 2003, we released our Galaxy™ Design and Discovery™ Verification platforms, which together provide complete implementation and verification solutions to our customers. In fiscal 2004, we delivered the Galaxy 2004 platform, providing full, cross-platform correlation in area, timing, power, signal integrity and test, as well as significant speed and capacity improvement. We also delivered substantial improvements to the capabilities, speed, capacity and accuracy of our Discovery Verification platform.

        To help our customers better manage time, cost and risk, we have also continued to invest in pre-designed, pre-verified and reusable intellectual property blocks our customers can use rather than build internally. These blocks include our DesignWare® Foundation Library of reusable, basic chip elements which can be pulled into designs during logic synthesis, our DesignWare Verification Library of reusable chip function models to accelerate simulation and verification, and our DesignWare Cores that implement many of the most important industry standards for digital and analog connectivity, including USB and PCI Express. We also provide professional services to assist our customers with their most difficult design challenges.

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        Finally, recognizing the challenges of manufacturing at feature widths smaller that the wavelength of light, and envisioning the benefits of taking manufacturing and yield issues into account during the design process, we have also continued to invest in our portfolio of Design for Manufacturing tools and technologies.

Organization

        We operate in a single segment and are currently organized into four primary groups: Implementation, Verification, Silicon Engineering and Solutions.

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Implementation Group: develops and markets the products included in the Galaxy Design Platform and related products.



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Verification Group: develops and markets the products included in the Discovery Verification Platform and related products.



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Silicon Engineering Group: focuses on our Design for Manufacturing initiatives and analog/mixed-signal design and verification products.



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Solutions Group: develops and markets our DesignWare® portfolio of pre-designed IP solutions for chip designers and provides turnkey IC design and on-site design assistance, among other services.

        Our other groups include Finance, Human Resources and Facilities, Marketing, Worldwide Sales and Worldwide Application Services.

Products and Services

        Our products and services focus on the principal needs of semiconductor designers and, at a business level, are divided into our Implementation, Verification, Silicon Engineering and Solutions groups described above. We provide financial information regarding our products and services under Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Results of Operations—Revenue—Product Groups, incorporated by reference here.

Implementation Group

        Galaxy Design Platform.    Our Galaxy Design Platform includes our logic synthesis, physical synthesis, physical design, timing analysis, signal integrity analysis and physical verification products, as well as certain analog and mixed-signal tools, including:

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Design Compiler® logic synthesis product, used by a broad range of IC design companies to optimize their designs for performance and area. With our Galaxy 2004 platform release, our Design Compiler product is up to three times faster than last year's release, has up to 25% more design capacity, and now supports System Verilog, an emerging hardware design language.



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Physical Compiler® physical synthesis product, which unites logic synthesis and placement functionality and addresses critical timing problems encountered in designing advanced ICs and SoCs. In fiscal 2004, we significantly improved the Physical Compiler product's run time and capacity.



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Module Compiler™ data path design product, which allows designers to reuse their datapath structures to obtain the best implementation for their designs.



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Power Compiler™ power management product, which helps designers manage and verify power consumption at different stages of the design process. The 2004 version of our Power Compiler product is up to ten times faster than the previous version.

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DFT Compiler™ design testing product, which inserts functional and test logic required to enable efficient, high-coverage testing of the chip after manufacture.



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JupiterXT™ design planning or floorplanning product, that allows designers to quickly partition their chip design into functional blocks that can be separately optimized for logic and physical design. The 2004 version of our JupiterXT product has two times the capacity, and creates a detailed floorplan three times faster, than the previous version..



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Apollo™ basic physical design product used for the placement and routing of a chip.



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Astro™ advanced physical design system, which enables optimization, placement and routing while concurrently accounting for physical effects. Our fiscal 2004 release of the Astro tool runs up to two times faster and has up to a 40% increase in capacity.



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PrimeTime®/PrimeTime® SI timing analysis products that measure and analyze the speed at which a design will operate when it is fabricated. The PrimeTime SI tool analyzes the effect of cross-talk and noise on timing, an increasingly important issue at chip geometries below 180 nanometers. The 2004 version of our PrimeTime tool runs up to three times faster and has up to three times the capacity as the prior version.



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Tetra Max® test pattern generation product family which automatically generates high-quality test vectors to improve the design process.



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Star-RCXT™ extraction solution for analyzing IC layout data and determining key electrical characteristics of a chip, such as capacitance and resistance.



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Hercules™ physical verification product family, which performs hierarchial design-rule checking, electrical rule checking, and layout versus schematic verification. During fiscal 2004, we delivered a faster version of the Hercules tool with higher multi-CPU scalability and broader foundry support.



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Milkyway™ Database, a common design data repository which enables better interoperability among implementation and analysis tools. Storing design data in this single database with rapid read/write access can reduce data translation times between tools and inconsistent interpretations of diverse data. Interfaces to our open Milkyway database have been made available to our customers and other EDA vendors to reduce integration costs for our customers and advance tool interoperability in the industry.

        The Galaxy Design Platform provides our customers a single, integrated IC design solution based on leading individual products and incorporating common libraries and consistent timing, delay calculation and constraints throughout the design process. The platform uses our open Milkyway database and allows designers the flexibility to integrate internally developed and third-party tools. With this advanced functionality, common foundation and flexibility, our Galaxy Design Platform helps reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC designs. During fiscal 2004, we released the Galaxy 2004 platform, the latest version of the Galaxy Design Platform, which delivers significantly improved quality of results, time to results and cost of results through greater correlation among the platform's individual products in addressing area, timing, power, signal integrity and test issues. We also introduced our Galaxy Power solution in fiscal 2004, offering designers the ability to improve the power efficiency of their ICs.

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Verification Group

        Discovery Verification Platform.    Our Discovery Verification Platform includes our verification and simulation products. The increasing size and complexity of today's ICs and SoCs have vastly increased the time and effort required to verify chip designs, with verification estimated to consume 60% to 70% of total design time. As a result, reducing verification "risk" (i.e. minimizing the possibility of finding design "bugs" when the ICs are delivered from the foundry) has become increasingly important to customers. To manage and reduce this verification risk, our Discovery platform combines our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to significantly improve the speed, breadth and accuracy of our customers' verification efforts.

        Our Discovery Verification Platform includes the following principal products:

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VCS® functional verification product, the engine of the Discovery Verification Platform and often used in simulation "farms" consisting of hundreds of computers. The VCS product includes technologies that support model development, testbench creation, coverage feedback and debugging techniques. Our fiscal 2004 release of the VCS product expands support of our Vera® product, making testbench automation native to VCS, and helping post a two to five times improvement in runtime.



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System Studio system level design product focused on system-level algorithm and architecture design and analysis, as well as the interaction between software and hardware and permits designers to model various architectural alternatives for their chips at a system level.



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Vera® testbench generator, which automates the creation of testbenches, custom models that provide simulation inputs and respond to simulated outputs from the design during verification. Automating this process significantly improves verification quality. The 2004 release of the Vera product is up to 10 times faster than its predecessor and is also available native to the VCS product, providing increased productivity benefits.



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LEDA® design rule checker, which enhances a designer's ability to check a design to ensure it can be for synthesized, simulated, tested and reused.



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Formality® formal verification solution, which compares two versions of a design to determine if they are equivalent. The use of formal verification reduces the need to perform functional verification, which is substantially more time-consuming, thus potentially saving a significant amount of time in the overall design process.



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Magellan™ hybrid formal verification product, which combines functional and formal verification technologies to allow engineers to find deep, corner-case design defects during verification.



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NanoSim® simulation and analysis product for analog and mixed signal verification, which offers circuit simulation, timing and power analysis in a single solution. The NanoSim product is a key component of our Discovery AMS verification solution.



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HSPICE® circuit simulator, which offers high-accuracy, transistor-level circuit simulation, thereby enabling designers to better predict the timing, power consumption and functionality of their designs. During fiscal 2004, we announced enhancements to the HSPICE tool resulting in significant improvements in performance and support for high-frequency and RF IC designs.



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Verification IP reusable IP that are designed to test specific functions and adherence to industry protocols in an IC design, which we believe is becoming increasingly important to more quickly achieving verification sign-off.

        In fiscal 2004, we delivered the Discovery AMS solution, a subset of our verification technologies optimized to perform verification on analog and mixed signal designs.

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Silicon Engineering Group

        Our Silicon Engineering Group develops and markets our products and initiatives relating to design for manufacturing and analog/mixed signal IC design and verification.

        Design for Manufacturing.    We offer a variety of products and technologies used at the intersection of IC design and manufacturing which address a number of issues, principally the need to precisely model structures in small geometry ICs and the problems encountered when using photolithography techniques to manufacture ICs containing feature dimensions smaller than the wavelength of light during production. These products are designed to enhance yield, which is becoming increasingly challenging as chip geometries continue to shrink. In addition to our Hercules product, described above under the Galaxy platform our Design for Manufacturing initiatives include our:

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TCAD products, which precisely model individual structures or devices within an IC design to help ensure manufacturability at small geometries. We see TCAD tools as increasingly important to help customers shorten the time to ramp up their production yields, and therefore reduce their manufacturing costs. In this regard, we have made significant investments to expand our TCAD offering, including our November 2004 acquisition of ISE Integrated Systems Engineering AG, a privately-held Swiss company which offered various TCAD products, including three dimensional devise simulators. We also introduced our Taurus Process Atomistic product which models processes at the atomic level for improved performance.



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Proteus OPC/InPhase optical proximity correction (OPC) products which embed and verify corrective features in an IC design and masks to improve manufacturing results for subwavelength feature width design. OPC changes mask geometries to compensate for distortions caused by optical diffraction and resist process effects. During fiscal 2004, we announced improvements to Proteus to provide near linear scalability.



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Phase Shift Masking Technologies consist of mask design techniques that use optical interference to improve depth-of-field and resolution in subwavelength photolithography for designs at 90 nanometers and below.



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SiVL® (Silicon versus Layout) layout verification product that verifies the layout of a subwavelength IC against the silicon it is intended to produce by reading in the layout and simulating lithographic process effects, including optical, resist and etch effects.



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CATS® mask data preparation product that takes a final IC design and "fractures" or "breaks" it into the physical features that will be included in the photomasks to be used in manufacturing.



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Virtual Stepper® mask qualification product, which checks mask quality and analyzes printability of mask defects, helping to separate true defects from nuisance defects.

        Analog and Mixed-Signal Tools.    The Silicon Engineering Group also manages a number of products described above and functionally included in our Galaxy and Discovery platforms that have advanced analog and mixed-signal design capabilities. These products include the NanoSim and HSPICE circuit simulators. In addition, this category includes our Cosmos™ product, which uses schematic-driven layout technology to place and route full-custom ICs, and our Circuit Explorer optimization and analysis product for complex analog designs.

Solutions Group

        Synopsys' Solutions Group includes our portfolio of IP products and components and our Professional Services Group.

        Intellectual Property Products.    As IC designs continue to grow in size, reusing proven design blocks has become an increasingly important way to reduce overall design cost and cycle time. Because

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verification accounts for such a large proportion of total chip design time, reusing pre-designed and verified IP components can keep projects on schedule by ensuring that the "designed in" portions of the chip are "pre-verified" and thus will not contain errors. The ability to reuse such IP allows IC companies to focus their design teams on designing the chip features that will give its products a competitive advantage. For these reasons, IC designers are consolidating their IP purchases from fewer vendors who can provide a reliable, comprehensive portfolio of proven IP.

        Our IP products include:

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DesignWare Foundation Library is an extensive library of basic chip elements (for example, adders and multipliers) which Design Compiler incorporates into the design during the logic synthesis stage.



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DesignWare Verification Library is our library of popular chip function models used during the verification process of chip design.



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DesignWare Cores are pre-designed and pre-verified digital and mixed-signal design blocks that implement many of the most important industry standards, including USB (1.1, 2.0 and On-The-Go), PCI (PCI, PCI-X and PCI Express), Ethernet and JPEG. During fiscal 2004, we announced availability of DesignWare PCI Express physical layer IP core, enabling lower cost ICs. We also acquired Accelerant Networks, Inc., giving our customers access to SERDES technology and additional connectivity IP solutions. Finally, during the year we acquired Cascade Semiconductor Solutions, Inc., adding their root-and-switch port IP. As a result, we believe we offer the industry's most complete PCI Express portfolio.

        Professional Services.    We provide a comprehensive portfolio of consulting services covering all critical phases of the SoC development process, as well as systems development in wireless and broadband applications. We offer customers a variety of engagement models, from on-site design assistance to help our customers design, verify and/or test their chips and improve their design processes, to full turnkey development and training.

Customer Service and Technical Support

        A high level of customer service and support is critical to the adoption and successful use of our products. We provide technical support for our products through both field- and corporate-based application engineering groups. Customers who purchase Technology Subscription Licenses (TSLs) receive software maintenance services bundled with their license fee. Customers who purchase term licenses and perpetual licenses may purchase these services separately. See Product Sales and Licensing Agreements below.

        Software maintenance services include minor product enhancements we develop, bug fixes and access to our technical support center for primary support. Software maintenance also includes access via electronic mail and the World Wide Web to SolvNet®, our web-based support solution that lets customers quickly seek answers to design questions or more insight into design problems. Our SolvNet solution gives customers access to Synopsys' complete design knowledge database using sophisticated information retrieval technology. Updated daily, it includes documentation, design tips and answers to user questions. Customers can also engage, for additional charges, our application consultants, our worldwide network of product experts, for additional support needs.

Customer Education Services

        We offer training workshops designed to increase customer design productivity while using our products. Workshops cover Synopsys products and methodologies used in our design and verification flows, as well as specialized modules addressing system design, logic design, physical design, simulation and test. We offer regularly scheduled workshops in Mountain View, California; Austin, Texas;

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Marlboro, Massachusetts; Reading, England; Rungis, France; Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other locations. We also schedule on-site workshops worldwide at our customers' facilities or other locations. Approximately 8,750 engineers attended Synopsys workshops during fiscal 2004, compared to approximately 8,500 in fiscal 2003.

Product Warranties

        We generally warrant our products to be free from defects in media and to substantially conform to material specifications for a period of 90 days. We also typically provide our customers limited indemnities with respect to claims that their use of our design and verification software products infringe on United States patents, copyrights, trademarks or trade secrets. We have not experienced material warranty or indemnity claims to date, although we are currently defending some of our customers against claims that their use of one of our products infringes a patent held by a Japanese electronics company.

Support for Industry Standards

        We actively create and support standards that will help our customers increase productivity, improve interoperability of tools from different vendors, and solve design problems. Standards in the EDA industry can be established by formal accredited committees, by licensing made available to all, or through open source licensing.

        Synopsys' products support many formal standards, including the most commonly used hardware description languages, VHDL, Verilog HDL, SystemVerilog and SystemC, as well as numerous industry standard data formats for the exchange of data between our tools, other EDA vendor's products and applications customers develop internally.

        Synopsys is a board member and/or participant in the following major EDA standards organizations:

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Accellera, a not-for-profit formal standards organization that drives language-based standards for systems, semiconductor, and design tool companies;



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the interoperability committee of the EDA Consortium, which helps promote quality and interoperability among EDA products from different vendors;



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the Institute of Electrical and Electronics Engineers (IEEE), a non-profit, technical professional association and a leading developer of global industry standards;



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the Virtual Socket Interface Alliance (VSIA), an industry group that promotes standards that facilitate the integration and reuse of functional blocks of intellectual property; and



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the Open SystemC Initiative (OSCI), a non-profit organization that manages SystemC, a language developed by Synopsys and donated to OSCI, with representation from the systems, semiconductor, IP, embedded software and EDA industries.

        Synopsys' TAP-in^SM program provides interface standards to all companies through an open source licensing model. Synopsys manages changes and enhancements that come from the community of licensees. Synopsys, other EDA companies and EDA customers use these standards to facilitate interoperability of their tools. The standards offered through our TAP-in program include our Liberty™ format for library modeling, SDC for design constraints, SAIF for switching activity, our OpenVera® language for hardware verification, and Open MAST for electromechanical design modeling. Synopsys' common database, Milkyway, is available for tool integration by EDA vendors through our MAP-in^SM program.

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        Synopsys' products are written mainly in the C and C++ languages and utilize industry standards for graphical user interfaces. Our software runs under UNIX operating systems, such as Solaris and HP-UX, and under the RedHat Linux operating system. Synopsys' products run on the most widely used hardware platforms, including those from Sun Microsystems, Hewlett-Packard, IBM and PCs that are based upon Intel and AMD microprocessors.

Sales, Distribution and Backlog

        We market our products and services primarily through direct sales in the United States and principal foreign markets. We typically distribute our products and documentation to customers electronically, but provide physical media (i.e. CD-ROMs) when requested by the customer. We employ highly skilled engineers and technically proficient sales persons in order to understand our customers' needs and explain and demonstrate the value of our products.

        We have sales/support centers throughout the United States, in addition to our Mountain View, California headquarters. Outside the United States, we have sales/support offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People's Republic of China, Singapore, South Korea, Sweden, Taiwan and the United Kingdom. Our foreign headquarters is located in Dublin, Ireland. Our offices are further described under Part I, Item 2. Properties.

        In limited circumstances, we have used distributors to assist us in the sale of certain products in specified markets. See Note 12 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data for additional information about one of our former distributors.

        In fiscal 2004, 2003 and 2002, foreign revenues represented 45%, 43% and 35%, respectively, of Synopsys' total revenue. Additional information relating to domestic and foreign operations is contained in Note 10 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data. Information relating to risks associated with foreign operations are described in Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Factors That May Affect Future Results—Stagnation of foreign economies, foreign exchange rate fluctuations or other international issues could adversely affect our performance.

        Historically, our orders and revenue have been lowest in our first quarter and highest in our fourth quarter, with a material decline between the fourth quarter of one fiscal year and the first quarter of the next fiscal year, although the timing of major license renewals can alter this typical trend. However, as a result of the shift in our license model, as more fully described in Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Results of Operations—Orders and Revenue Seasonality, we expect less revenue seasonality beginning in fiscal year 2005.

        Synopsys' aggregate non-cancelable backlog was approximately $1.48 billion on October 31, 2004, representing an approximately 8% decrease from the end of fiscal 2003. Aggregate non-cancelable backlog includes deferred revenue, operational backlog and financial backlog and excludes all items relating to consulting services. Deferred revenue represents that portion of orders for software products, license maintenance and other services which has been delivered and billed to the customer but on which the revenue has not yet been earned. Operational backlog consists of orders for software products sold under perpetual or term licenses and TSLs with customer-requested ship dates within three months that have not been shipped. Financial backlog consists of future installments under time-based licenses and maintenance which are not yet currently due and payable. Our aggregate backlog at the end of fiscal 2004 including consulting was approximately $1.53 billion, approximately 9% lower than at the end of fiscal 2003.

        We have not historically experienced material order cancellations.

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        See Item 13. Certain Relationships and Related Transactions for information concerning customers accounting for more than 10% of our revenue during fiscal 2004.

Research and Development

        Our future performance depends in large part on our ability to further integrate our design and verification platforms, maintain and enhance our current products, develop new products, and meet an expanding range of customer requirements. Research and development on existing and new products is primarily conducted within each product group. In addition, an Advanced Technology Group within Synopsys' Silicon Engineering Group explores new technologies and maintains strong research relationships outside Synopsys with both industry and academia.

        During fiscal 2004, 2003 and 2002, research and development expenses, net of capitalized software development costs, were $285.3 million, $285.9 million and $225.5 million, respectively. Synopsys capitalized software development costs were approximately $2.7 million, $2.6 million and $1.6 million in fiscal 2004, 2003 and 2002, respectively. We expect sales and marketing expense to increase slightly in fiscal 2005 as a result of increased headcount from acquisitions during fiscal 2004 and higher targeted incentive compensation.

Competition

        The EDA industry is highly competitive. We compete against other EDA vendors and against our customers' own design tools and internal design capabilities. In general, we compete principally on technology leadership, product quality and features (including ease-of-use), time-to-results, post-sale support, interoperability with our own and other vendors' products, price and payment terms.

        Our competitors include companies that offer a broad range of products and services, such as Cadence Design Systems, Inc. and Mentor Graphics Corporation, and companies that offer products focused on one or more discrete phases of the IC design process, such as Magma Design Automation, Inc. Since the recent semiconductor downturn, we have increasingly competed on the basis of payment terms and price. In certain situations, in order to win business we must offer substantial discounts on our products due to competitive factors. In other situations, we may lose potential business to a vendor offering a lower price.

Product Sales and Licensing Agreements

        We typically license our software to customers under non-exclusive license agreements that transfer title to the media only and restrict use of our software to specified purposes within specified geographical areas. The majority of our licenses are network licenses that allow a number of individual users to access the software on a defined network, including, in some cases, regional or global networks. License fees depend on the type of license, product mix and number of copies of each product licensed.

        Under certain circumstances, we provide our customers the right to exchange a portion of the software they initially license for other specified Synopsys products. For example, a customer may use our front-end design products for a portion of the license term and then exchange such products for back-end placement software for the remainder of the term in order to complete the customer's IC design. This practice helps assure the customer's access to the complete design flow needed to design its product. The customer's exchange of product for other existing products, when so provided under the customer agreement, does not alter the timing of recognition of the license fees paid by the customer, which is governed by our revenue recognition policies. The ability to offer this right to customers often gives us an advantage over competitors who offer a narrower range of products, because customers can obtain more of their design flow from a single vendor and because customers then have an opportunity to try additional Synopsys tools before licensing them separately. At the same

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time, because in such cases the customer need not obtain a new license and pay an additional license fee for the use of the additional products, the use of these arrangements could result in reduced revenue compared to licensing the individual products separately without exchange rights.

        We currently offer our software products under two license types: renewable TSLs and perpetual licenses. For a full discussion of these licenses, see Part II, Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations—Critical Accounting Policies and Results of Operations—Revenue Background.

        With respect to our DesignWare Core intellectual property products, we typically license those products to our customers under nonexclusive license agreements that provide usage rights for specific applications. Fees under these licenses are typically charged on a per design basis plus, in some cases, royalties.

        Finally, our professional services teams typically operate under consulting agreements with our customers with statements of work specific to each project.

Proprietary Rights

        Synopsys primarily relies upon a combination of copyright, patent, trademark and trade secret laws and license and nondisclosure agreements to establish and protect its proprietary rights. Our source code is protected both as a trade secret and as an unpublished copyrighted work. However, third parties may develop similar technology independently. In addition, effective copyright and trade secret protection may be unavailable or limited in certain foreign countries. We currently hold United States and foreign patents on some of the technologies included in our products and will continue to pursue additional patents in the future.

        Under our customer agreements and other license agreements, in many cases we offer to indemnify our customer if the licensed products infringe on a third party's intellectual property rights. As a result, we are from time to time subject to claims that our products infringe on these third party rights. For example, we are currently defending some of our customers against claims that their use of one of our products infringes a patent held by a Japanese electronics company. We believe this claim is without merit and will continue to vigorously pursue this defense.

Employees

        As of October 31, 2004, Synopsys had 4,378 full-time employees, with 2,940 based in North America and 1,438 based outside of North America. Our future financial results depend in part upon the continued service of our key technical and senior management personnel and our continuing ability to attract and retain highly qualified technical and managerial personnel. We participate in a dynamic industry, with significant start-up activity, and our headquarters is located in Silicon Valley, where competition for the most highly skilled technical, sales and management employees is intense.

Item 2. Properties

United States Facilities

        Synopsys' principal offices are located in four adjacent buildings in Mountain View, California, which together provide approximately 400,000 square feet of available space. This space is leased through February 2015. Within one half mile of these buildings, in Sunnyvale, California, Synopsys occupies approximately 200,000 square feet of space in two adjacent buildings under lease through April 2007, and approximately 72,000 square feet of space in a third building under lease through April 2007. We use these buildings for administrative, marketing, research and development, sales and support activities.

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        We own two buildings totaling approximately 230,000 square feet on approximately 43 acres of land in Hillsboro, Oregon. Only one of these buildings is occupied, and is used for administrative, marketing, research and development and support activities. In addition, we lease approximately 80,000 square feet of space in Marlboro, Massachusetts for sales and support, research and development and customer education activities. This facility is leased through January 2009.

        Synopsys owns a third building in Sunnyvale, California with approximately 120,000 square feet, which is leased to a third party through February 2009. Synopsys also owns 34 acres of undeveloped land in San Jose, California and 13 acres of undeveloped land in Marlboro, Massachusetts.

        Synopsys currently leases 32 other offices throughout the United States, primarily for sales and support.

International Facilities

        Synopsys leases approximately 45,000 square feet in Dublin, Ireland for its foreign headquarters and for research and development purposes. This space is leased through April 2026. In addition, Synopsys leases foreign sales and service offices in Canada, Denmark, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, the Netherlands, the People's Republic of China, Singapore, South Korea, Sweden, Taiwan and the United Kingdom. We also lease research and development facilities in Armenia, Canada, France, Germany, India, the Netherlands, the People's Republic of China, South Korea, Taiwan and the United Kingdom.

        As a result of acquisitions, we have assumed leases in a number of foreign and domestic locations. Following each acquisition, where feasible, we consolidate the acquired company's employees and operations into our existing local sites. In such cases, we generally seek to sublease the assumed space or negotiate with the landlord to terminate the underlying lease.

        We believe our properties are adequately maintained and suitable for their intended use and that our facilities have adequate capacity for our current needs.

Item 3. Legal Proceedings

        On August 25, 2004, a class action complaint entitled Kanekal v. Synopsys, Inc., et al., No. C-04-3580, was filed in federal district court for the Northern District of California against Synopsys and certain of our officers alleging violations of the Exchange Act. The complaint purports to be a class action lawsuit brought on behalf of persons who acquired Synopsys stock during the period of December 3, 2003 through August 18, 2004. The complaint alleges that the individual defendants caused Synopsys to make false and misleading statements about Synopsys' business, forecasts, and financial performance, and that certain Synopsys officers or employees sold portions of their stock holdings while in the possession of adverse, non-public information. The complaint does not specify the amount of damages sought. In November 2004, the Court appointed a lead plaintiff in the case. As a result, Synopsys expects the plaintiff to file an amended complaint in January 2005. Discovery has not commenced in the case and no trial date has been established. While management intends to defend against these federal securities claims vigorously, and Synopsys does not believe that this lawsuit will have a material effect on Synopsys' financial position, results of operations or cash flows, there can be no assurance as to the ultimate disposition of this lawsuit.

        After the end of fiscal 2004, and in connection with our December 1, 2004 announcement that we have signed agreements to acquire Nassda Corporation (Nassda) and to settle all outstanding litigation between the two companies, a class action complaint entitled Robert Israel v. Nassda Corporation, et. al., No. 4705695, was filed in the Court of Chancery of the State of Delaware naming Nassda, its directors and Synopsys as defendants. The complaint purports to be a class action lawsuit brought on behalf of shareholders of Nassda, other than the defendant directors and their affiliates, who allegedly

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would be injured or threatened with injury if the proposed acquisition of Nassda by Synopsys proceeded forward on the terms announced. The purported class action seeks to enjoin the transaction, or alternatively, damages. The complaint does not specify the amount of damages sought. Synopsys believes the claims in this purported class action are without merit, and intends to defend against them vigorously.

Item 4. Submission of Matters to a Vote of Security Holders

        No matters were submitted for a vote of security holders during the fourth quarter of fiscal 2004.

Executive Officers of the Registrant

        The executive officers of Synopsys and their ages as of December 31, 2004, were:

        Dr. Aart J. de Geus co-founded Synopsys and currently serves as Chairman of the Board of Directors and Chief Executive Officer. Since the inception of Synopsys in December 1986, he has held a variety of positions, including Senior Vice President of Engineering and Senior Vice President of Marketing. From 1986 to 1992, Dr. de Geus served as Chairman of the Board. He served as President from 1992 to 1998. Dr. de Geus has served as Chief Executive Officer since January 1994 and has held the additional title of Chairman of the Board since February 1998. He has served as a Director since 1986. From 1982 to 1986 Dr. de Geus was employed by General Electric Corporation, where he was the Manager of the Advanced Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E. from the Swiss Federal Institute of Technology in Lausanne, Switzerland and a Ph.D. in electrical engineering from Southern Methodist University.

        Dr. Chi-Foon Chan joined Synopsys as Vice President of Application Engineering & Services in May 1990. Since April 1997 he has served as Chief Operating Officer and since February 1998 he has

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held the additional title of President. Dr. Chan also became a Director of Synopsys in February 1998. From September 1996 to February 1998 he served as Executive Vice President, Office of the President. From February 1994 until April 1997 he served as Senior Vice President, Design Tools Group, and from October 1996 until April 1997 as Acting Senior Vice President, Design Re-Use Group. In addition, he has held the titles of Vice President, Engineering and General Manager, DesignWare Operations and Senior Vice President, Worldwide Field Organization. From March 1987 to May 1990, Dr. Chan was employed by NEC Electronics, where his last position was General Manager, Microprocessor Division. From 1977 to 1987, Dr. Chan held a number of senior engineering positions at Intel Corporation. Dr. Chan holds an M.S. and a Ph.D. in computer engineering from Case Western Reserve University.

        Steven K. Shevick joined Synopsys in July 1995 and currently serves as Senior Vice President, Finance and Chief Financial Officer. Mr. Shevick was appointed Senior Vice President and Chief Financial Officer in January 2003. From October 1999 to January 2003, he was Vice President, Investor Relations and Legal, General Counsel and Corporate Secretary. From March 1998 to October 1999, he was Vice President, Legal, General Counsel and Assistant Corporate Secretary. From July 1995 to March 1998 he served as Deputy General Counsel and Assistant Corporate Secretary. Mr. Shevick holds an A.B. from Harvard College and a J.D. from Georgetown University Law Center.

        Vicki L. Andrews joined Synopsys in May 1993 and currently serves as Senior Vice President, Worldwide Sales. Before holding that position, she served in a number of senior sales roles at Synopsys, including Vice President, Global and Strategic Sales, Vice President, North America Sales and Director, Western United States Sales. She has more than 18 years of experience in the EDA industry. Ms. Andrews holds a B.S. in biology and chemistry from the University of Miami.

        Dr. Raul Camposano has served as Senior Vice President, Chief Technology Officer and General Manager, Silicon Engineering Group since July 2004. Prior to that time, he was Senior Vice President and Chief Technology Officer from September 2000 to July 2004, and Senior Vice President, General Manager of the Design Tools Group from 1997 through September 2000. Prior to joining Synopsys in 1994, he directed the Design Technology Institute at the German National Research Center for Computer Science (GMD) and was a professor in the Department of Computer Science at the University of Paderborn, Germany. Between 1986 and 1991, Dr. Camposano worked at the IBM T.J. Watson Research Center. He was also a member of the research staff at the Computer Science Research Laboratory at the University of Karlsruhe. Dr. Camposano received a B.S.E.E. degree in 1977 and a diploma in electrical engineering in 1978 from the University of Chile and a Ph.D. in computer science from the University of Karlsruhe in 1981.

        John Chilton has served as Senior Vice President and General Manager of the Solutions Group of Synopsys since August 2003. Prior to that time, he was Senior Vice President and General Manager of the IP and Design Services Business Unit from 2001 to August 2003. From 1997 to 2001, Mr. Chilton served as Vice President and General Manager of the Design Reuse Business Unit. Mr. Chilton received an M.S.E.E. from the University of Southern California and a B.S.E.E. from University of California at Los Angeles.

        Janet S. Collinson has served as Senior Vice President, Human Resources and Facilities since August 2003. From September 1999 to August 2003 she was Vice President, Real Estate and Facilities. Prior to that time she served as Director of Facilities from January 1997 to September 1999. Ms. Collinson received a B.S. in Human Resources from California State University, Fresno.

        Dr. Antun Domic has served as Senior Vice President and General Manager of the Implementation Group since August 2003. Prior to that, Dr. Domic was Vice President and General Manager of the Nanometer Analysis and Test Group from 1999 to August 2003. Dr. Domic joined Synopsys in April 1997, having previously worked at Cadence Design Systems and Digital Equipment Corporation.

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Dr. Domic has a B.S. in Mathematics and Electrical Engineering from the University of Chile in Santiago, Chile, and a Ph.D. in Mathematics from the Massachusetts Institute of Technology.

        Manoj Gandhi has served as Senior Vice President and General Manager, Verification Group since August 2000. Prior to that he was Vice President and General Manager of the Verification Tools Group from July 1999 to August 2000. Prior to that time, he was Vice President of Engineering from December 1997 until July 1999. He holds a B.S. in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and an M.S. in Computer Science from the University of Massachusetts, Amherst.

        Jay N. Greenberg joined Synopsys in November 2004 as Senior Vice President, Marketing. From March 2003 until joining Synopsys, Mr. Greenberg was President of Green Mountain Solutions, a consulting firm that he also founded. From March 1999 to March 2003 Mr. Greenberg was employed by Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC), where he held the positions of Vice President of Business Development and Vice President of Strategic Marketing. Mr. Greenberg served as Vice President and Senior Partner at Thomas Group, Inc., a consulting firm, from 1987 through 1998. Mr. Greenberg has also held executive, management and technical positions at Memorex, Amdahl and EDS. Mr. Greenberg holds a B.A. from the University of the Pacific in Stockton, California.

        Deirdre Hanford has served as Senior Vice President of Worldwide Applications Services since December 2002. Prior to that time, she was Senior Vice President, Business and Market Development of Synopsys from September 1999 to December 2002. From October 1998 until September 1999, she served as Vice President, Sales for Professional Services and prior to that as Vice President, Corporate Applications Engineering from April 1996 to September 1999. Ms. Hanford received a B.S.E.E. from Brown University and an M.S.E.E. from University of California at Berkeley. Ms. Hanford sits on the American Electronics Association's national board of directors.

        Rex S. Jackson joined Synopsys in February 2003 as Vice President, General Counsel and Corporate Secretary. Prior to joining Synopsys, Mr. Jackson was an investment director with Redleaf Group, Inc., an early stage venture capital firm, from April 2000 through December 2001, and President and CEO of Atlantes Services, Inc., a Redleaf portfolio company, from December 2001 through January 2003. Prior to joining Redleaf, from August 1998 to April 2000, Mr. Jackson was Vice President and General Counsel of AdForce, Inc., a provider of ad management and delivery services on the Internet. Prior to joining AdForce, Mr. Jackson served as Vice President, Business Development and General Counsel of Read-Rite Corporation, a manufacturer of thin film recording heads for the disk and tape drive industries from 1996 to 1998, and as Vice President and General Counsel from 1992 to 1996. Mr. Jackson holds an A.B. degree from Duke University and a J.D. degree from Stanford University.

        There are no family relationships among any Synopsys executive officers or directors.

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PART II

Item 5. Market for Registrant's Common Equity, Related Stockholder Matters and Issuer Purchases of Equity Securities

        The table below sets forth information regarding repurchases of Synopsys common stock by Synopsys during the fiscal quarter ended October 31, 2004.

        All shares were purchased pursuant to a $500 million stock repurchase program originally approved by Synopsys' Board of Directors in July 2001 and renewed in December 2002 and December 2003. Funds are available until expended or until the program is suspended by the Chief Financial Officer or the Board of Directors. Effective and announced on December 1, 2004 the Board of Directors renewed the stock repurchase program, authorizing up to $500 million in additional share repurchases, not including amounts expended prior to such date.

        The remaining information required by Item 5 is set forth in Note 14 of our Notes to Consolidated Financial Statements in Part II, Item 8. Financial Statements and Supplementary Data, incorporated by reference here.

Item 6. Selected Financial Data

Financial Summary

(1)

Synopsys has a fiscal year that ends on the Saturday nearest October 31. Fiscal 2004, 2003, 2002, and 2000 were 52-week years while fiscal 2001 was a 53-week year. For presentation purposes, the consolidated financial statements refer to the calendar month end.

(2)

Includes charges of $1.6 million, $19.8 million, $87.7 million, and $1.7 million for fiscal 2004, 2003, 2002, and 2000, respectively, for in-process research and development. Fiscal 2002 includes merger-related and other costs of $33.5 million and insurance premium costs of $335.8 million related to the Avant! merger.

(3)

Per share data for all periods presented have been adjusted to reflect Synopsys' two-for-one stock split completed on September 23, 2003.

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Item 7. Management's Discussion and Analysis of Financial Condition and Results of Operations

Overview

        The following summary of our financial condition and results of operations is qualified in its entirety by the more complete discussion contained in this Item 7 and by the risk factors set forth below under the caption entitled "Facto