Back to GetFilings.com

UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549

FORM 10-K

Commission File Number: 000-18032

LATTICE SEMICONDUCTOR CORPORATION
(Exact name of Registrant as specified in its Charter)

Registrant's telephone number, including area code: (503) 268-8000

Securities registered pursuant to Section 12(b) of the Act: None
Securities registered pursuant to Section 12(g) of the Act:

Title of Class

Common Stock, $.01 par value

        Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes  ý    No  o

        Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. ý

        Indicate by check mark whether the Registrant is an accelerated filer (as defined in Rule 12b-2 of the Act). Yes  ý    No  o

        As of June 27, 2003 (the last business day of the Registrant's second quarter of fiscal 2003), the aggregate market value of the shares of voting stock (Common Stock) of the Registrant held by non-affiliates was approximately $632.9 million based on the last sales price of the Registrant's Common Stock on the Nasdaq National Market on such date. Shares of Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock have been excluded in that such persons may be deemed affiliates. This determination of affiliate status is not necessarily a conclusive determination for other purposes.

        As of March 29, 2004, 113,115,442 shares of the Registrant's common stock were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

        Portions of the definitive proxy statement of the Registrant to be filed pursuant to Regulation 14A for the 2004 Annual Meeting of Stockholders to be held on May 11, 2004 are incorporated by reference in Part III hereof.

LATTICE SEMICONDUCTOR CORPORATION
FORM 10-K
ANNUAL REPORT
TABLE OF CONTENTS

1

Forward-Looking Statements

        This Annual Report on Form 10-K contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Exchange Act. Any statements about our expectations, beliefs, plans, objectives, assumptions or future events or performance are not historical facts and may be forward-looking. We use words or phrases such as "anticipates," "believes," "estimates," "expects," "intends," "plans," "projects," "may," "will," "should," "continue," "ongoing," "future," "potential" and similar words or phrases to identify forward-looking statements.

        Forward-looking statements involve estimates, assumptions, risks and uncertainties that could cause actual results to differ materially from those expressed in them. Among the key factors that could cause our actual results to differ materially from the forward-looking statements are delay in product or technology development, change in economic conditions of the various markets we serve, lack of market acceptance or demand for our new products, dependencies on silicon wafer suppliers and semiconductor assemblers, the impact of competitive products and pricing, opportunities or acquisitions that we pursue, the availability and terms of financing, and the other risks that are described herein and that are otherwise described from time to time in our filings with the Securities and Exchange Commission, including but not limited to the items discussed in "Factors Affecting Future Results" set forth in "Management's Discussion and Analysis of Financial Condition and Results of Operations" in Item 7 of this report. You should not unduly rely on forward-looking statements because our actual results could differ materially from those expressed in any forward-looking statements made by us. Further, any forward-looking statement applies only as of the date on which it is made. We are not required to update any forward-looking statement or statements to reflect events or circumstances after the date on which such statement is made or to reflect the occurrence of unanticipated events.

Item 1. Business.

        Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices, or PLDs, and related software. Programmable logic devices are widely-used semiconductor components that can be configured by end customers as specific logic circuits, and thus enable shorter design cycle times and reduced development costs. Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, automotive, medical, consumer and military end markets.

        Lattice was incorporated in Oregon in 1983 and reincorporated in Delaware in 1985. Our principal offices are located at 5555 N.E. Moore Court, Hillsboro, Oregon 97124, our telephone number is (503) 268-8000 and our website can be accessed at www.latticesemi.com. Information contained or referenced on our website is not incorporated by reference and does not form a part of this Annual Report on Form 10-K.

        We report based on a 52 or 53 week year ending on the Saturday closest to December 31. For ease of presentation, we have adopted the convention of using March 31, June 30, September 30 and December 31 as period end dates for all financial statement information. Our 2003 fiscal year was a 53-week year.

PLD Market Background

        Three principal types of digital integrated circuits are used in most electronic systems: microprocessors, memory and logic. Microprocessors are used for control and computing tasks, memory is used to store programming instructions and data, and logic is employed to manage the interchange and manipulation of digital signals within a system. Logic contains interconnected groupings of simple logical "and" and logical "or" functions, commonly described as "gates." Typically, complex combinations of individual gates are required to implement the specialized logic functions required for

2

systems applications. While system designers use a relatively small variety of standard products to meet their microprocessor and memory needs, they require a wide variety of logic products in order to achieve end product functionality and differentiation.

        Logic circuits are found in a wide range of today's digital electronic equipment including communications, computing, industrial, automotive, medical, consumer and military systems. According to World Semiconductor Trade Statistics ("WSTS"), a semiconductor industry association, logic accounted for approximately 26% of the estimated $140 billion worldwide digital integrated circuit market in 2003. The logic market encompasses, among other segments, standard logic, custom-designed application specific integrated circuits, or ASICs, which include conventional gate-arrays, standard cells and full custom logic circuits, and PLDs.

        Manufacturers of electronic equipment are challenged to bring differentiated products to market quickly. These competitive pressures often preclude the use of custom-designed ASICs, which generally entail significant design risks, non-recurring costs and time delays. Standard logic products, an alternative to custom-designed ASICs, limit a manufacturer's flexibility to adequately customize an end system. PLDs address this inherent dilemma. PLDs are standard products, purchased by systems manufacturers in a "blank" state, that can be custom configured into a virtually unlimited number of specific logic functions by programming the device with electrical signals. PLDs give system designers the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. Certain PLD products, including our own, are reprogrammable, meaning that the logic configuration can be modified, if needed, after the initial programming. ISP™ and XP™ PLDs, pioneered by us, extend the flexibility of standard reprogrammable PLDs by allowing the system designer to configure and reconfigure logic functions using system power supplies and without removing the PLD from the system board.

        According to WSTS, the PLD market was approximately $2.7 billion in 2003. Within this market there are two main segments, complex PLD ("CPLD") and field programmable gate array ("FPGA"), each representing a distinct silicon architectural approach. In 2003, CPLD was a $0.5 billion market while FPGA was a $2.0 billion market.

        Products based on the two alternative PLD architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture. CPLDs are characterized by a regular building block structure of wide-input logic cells, called macrocells, and use of a centralized logic interconnect scheme. FPGAs are characterized by a narrow-input logic cell and use a distributed interconnect scheme. FPGAs may also contain dedicated blocks of fixed circuits such as memory, high-speed interface logic or processing engines. Although CPLDs and FPGAs are typically suited for use in distinct types of logic applications, we believe that a substantial portion of PLD customers utilize both CPLD and FPGA architectures within a single system design, partitioning logic functions across multiple devices to optimize overall system performance and cost.

Technology

        We believe that our proprietary E²CMOS® technology is the preferred process technology for CPLD products due to its inherent performance, reprogrammability and testability benefits. E²CMOS technology, through its fundamental ability to be programmed and erased electronically, serves as the foundation for our ISP and XP products.

        We pioneered the development of in-system programmability ("ISP™"), which has become an industry standard feature in the PLD market. Our ISP devices can be configured and reconfigured by a system designer without being removed from the printed circuit board. These ISP devices can allow customers to reduce design cycle times, accelerate time to market, reduce prototyping costs, reduce manufacturing costs and lower inventory requirements. Our ISP devices can also provide customers the

3

opportunity to perform simplified and cost-effective field reconfiguration through a data file transferred by computer disk or serial data signal.

        In 2002, we introduced XP, or extended programmability, technology. Traditional PLDs have been based on either volatile SRAM technology, which is infinitely reconfigurable, or non-volatile E²CMOS technology, which is reprogrammable but not infinitely reconfigurable. Both these technologies require compromises on the part of the customer. XP technology, based on an embedded flash process, is the only programming technology that enables a programmable logic device to be both non-volatile and infinitely reconfigurable.

Products

        We strive to offer innovative and differentiated programmable solutions based on our proprietary technology.

CPLD Products

        Since 1992, we have focused on developing a leadership portfolio of CPLD products and increasing the percentage of our overall revenue derived from this attractive market. During 2003, approximately 69% of our revenue was derived from CPLD products, as compared to 69% in 2002 and 76% in 2001. At present, we offer the industry's broadest line of CPLDs based on our numerous families of ispLSI® and ispMACH® products. In the future, we plan to continue to introduce new families of innovative CPLD products, as well as improve the performance and reduce the manufacturing cost of our existing product families based on market needs.

        Our newest CPLD product families use innovative architectures and are targeted towards the low voltage portion of the market. We believe that our multiple families of leadership CPLD products provide us a competitive advantage in this market. The key features of these families are described in the table below:

        In addition to high performance, the ispMACH 4000Z family features a new architecture optimized to ensure ultra-low power consumption. Devices within this new family, targeted toward handheld and portable equipment, typically operate using 10-15 microamps of current while in standby mode.

FPGA Products

        In 2002, we entered the FPGA market as a result of our acquisition of the FPGA business of Agere and the introduction of an internally developed product family. During 2003, approximately 18% of our revenue was derived from FPGA products, as compared to 12% in 2002 and 0% in 2001. At present we offer the FPGA product families described below. In the future, we plan to introduce new

4

families of innovative, high performance and higher density FPGAs. Key features of our ORCA FPGA families are described in the table below:

        In addition, we offer a family of field programmable system chips ("FPSC"). FPSCs, which combine generic FPGAs with embedded intellectual property cores on a single programmable chip, offer customers the ability to quickly implement complex system-level designs in a flexible manner. Currently, we offer seven FPSC devices, the ORT82G5, ORT42G5, ORT8850L, ORT8850H, ORLI10G, ORSO82G5 and ORSPI4, based on the ORCA 4 FPGA platform. These devices incorporate high-speed interface protocols, offering up to 4.25 Gbs SERDES, and other application-specific circuit blocks that allow customers to develop high performance designs to implement 10 Gigabit ethernet and SONET applications within advanced communications systems.

        During 2002, we introduced two new FPGA product families utilizing our innovative XP, or extended programmability technology. The ispXPLD family, based on a hybrid architecture, combines the benefits of a wide-input CPLD logic cell with the availability of abundant memory resources. Offering up to 1024 logic macrocells, propagation delays as low as 4 nanoseconds and up to 512 Kb of memory, the ispXPLD offers customers a new alternative for high density logic designs. The ispXPGA family, based on a mainstream FPGA architecture, offers densities of up to 1.25 million logic gates and brings the benefits of XP technology to the FPGA marketplace.

        We also offer an additional FPGA product family, ispGDX, that targets a unique aspect of the programmable logic market. This family extends in-system programmability to the circuit board level using an innovative digital cross-point switch architecture. Offered with propagation delays as low as 3.0 nanoseconds, up to 256 input/output pins and complete pin-to-pin signal routing, ispGDX products are targeted towards digital signal interconnect and interface applications.

Other Products

        We also offer programmable analog and mixed signal products as we believe these devices provide an opportunity to extend our proprietary technology to an untapped potential market. The innovative architecture of our ispPAC® products allows designers to quickly and easily program resistor and capacitor values, gain and signal polarity and circuit interconnect to implement a wide variety of functions. Our ispPAC products are targeted towards power management, filtering and signal conditioning applications and can replace numerous discrete analog components. ispPAC designs are implemented and programmed via a personal computer using our software development tool, PAC-Designer®.

Software Development Tools

        All of our products are supported by our ispLEVER™ 3.1 software development tool suite. This latest version of ispLEVER software supports all of our CPLD and FPGA product families. Supporting both the PC and UNIX platforms, ispLEVER allows our customers to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign input/output pins, designate critical paths, debug, execute automatic timing-driven place and route tasks and download a program to one of our ISP devices. Seamlessly integrated with third-party electronic design automation environments, ispLEVER provides a front-to-back design flow that leverages a customer's prior investment in tools offered by Aldec, Cadence, Mentor Graphics, Synopsys and Synplicity. In the future, we plan to continue to enhance and expand the capability of our software development tool suite.

5

        We also provide a variety of software algorithms that support in-system programming of our ISP devices through an interface cable or directly from a system microprocessor.

Low Density PLD Products—SPLD

        We offer the industry's broadest line of low-density CMOS PLDs, or SPLDs, based on our 18 families of GAL® products offered in over 200 speed, power, package and temperature range combinations. These devices range in complexity from approximately 200 to 1,000 logic gates and are typically assembled in 20-, 24- and 28-pin standard dual in-line packages and in 20- and 28-pin standard plastic leaded chip carrier packages. We offer the standard 16V8, 20V8 and 22V10 architectures in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. In addition, we offer several proprietary extension architectures, the isp22V10, 6001/2, 16VP8, 16V8Z, 18V10, 20VP8, 20V8Z, 20RA10, 20XV10 and 26V12, each of which is optimized for specific applications. We also offer a full range of 3.3-volt standard architectures, the isp22LV10, 16LV8, 20LV8, 22LV10 and 26CLV12, in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry. During 2003, approximately 13% of our revenue was derived from SPLD products, as compared to 19% in 2002 and 24% in 2001.

Product Development

        We place substantial emphasis on new product development and believe that continued investment in this area is required to maintain our competitive position. Our product development activities emphasize new proprietary products, enhancement of existing products and process technologies and improvement of software development tools. Product development activities occur in Hillsboro, Oregon; San Jose, California; Broomfield, Colorado; Naperville, Illinois; Bethlehem, Pennsylvania; Austin, Texas; Salt Lake City, Utah; Shanghai, China; and Corsham, England.

        Research and development expenses were $71.7 million in 2001, $85.8 million in 2002 and $87.1 in 2003. We expect to continue to make significant future investments in research and development.

Operations

        We do not manufacture our own silicon wafers. We maintain strategic relationships with large semiconductor foundries to source our finished silicon wafers. This strategy allows us to focus our internal resources on product, process and market development, and eliminates the fixed cost of owning and operating manufacturing facilities. We are also able to take advantage of the ongoing advanced process technology development efforts of semiconductor foundries. In addition, all of our assembly operations and most of our test operations are performed by outside suppliers. We perform certain test operations and reliability and quality assurance processes internally. We have achieved an ISO 9001 quality certification, which is an indication of our high internal operational standards.

Wafer Fabrication

        We source silicon wafers from our foundry partners, Seiko Epson in Japan, United Microelectronics Corporation ("UMC") in Taiwan and Chartered Semiconductor Manufacturing, Ltd. ("Chartered Semiconductor") in Singapore, pursuant to agreements with each company and their respective affiliates. We negotiate wafer volumes, prices and other terms with our foundry partners and their respective affiliates on a periodic basis.

        In March 2004 we announced that we will also be sourcing wafers on advanced process technologies from Fujitsu Limited in Japan.

6

Assembly

        After wafer fabrication and initial testing, we ship wafers to independent subcontractors for assembly. During assembly, wafers are separated into individual die and encapsulated in plastic or ceramic packages. Presently, we have qualified long-term assembly partners in China, Malaysia, the Philippines, South Korea, and Taiwan.

Testing

        We electrically test the die on each wafer prior to shipment for assembly. Following assembly, prior to customer shipment, each product undergoes final testing and quality assurance procedures. Final testing on certain products is performed by independent contractors in China, Malaysia, the Philippines, South Korea and Taiwan, and at our Oregon facility.

Marketing, Sales and Customers

        We sell our products directly to end customers through a network of independent manufacturers' representatives and indirectly through a network of independent distributors. We also employ a direct sales management and field applications engineering organization to support our end customers and indirect sales resources. Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, automotive, medical, consumer and military end markets.

        As of December 2003, we used 18 manufacturers' representatives and two distributors, Arrow Electronics, Inc. and Avnet Inc., in North America. We have also established export sales channels in over 30 foreign countries through a network of over 30 sales representatives and distributors. Approximately two-thirds of our North American sales and the majority of our export sales are made through distributors.

        We protect each of our North American distributors and some of our foreign distributors against reductions in published prices, and expect to continue this policy in the foreseeable future. We also allow returns from these distributors of unsold products under certain conditions. For these reasons, we do not recognize revenue until products are resold by these distributors to an end customer.

        We provide technical and marketing support to our end customers with engineering staff based at our headquarters, product development centers and selected field sales offices. We maintain numerous domestic and international field sales offices in major metropolitan areas.

        Export sales as a percentage of our total revenue were 54% in 2001, 60% in 2002 and 68% in 2003. Both export and domestic sales are denominated in U.S. dollars, with the exception of sales to Japan, which are denominated in yen. If our export sales decline significantly there would be a material adverse impact on our business and results of operations.

        Our products are sold to a large and diverse group of customers. No individual end customer accounted for more than 10% of total revenue in 2001, 2002 or 2003. No export sales to any given country accounted for more than 10% of total revenue in 2001 or 2002. Export sales to Japan were approximately 11% of revenue in 2003, while export sales to China and Taiwan were each slightly less than 10%.

Backlog

        Our backlog of scheduled and released orders as of December 31, 2003 was approximately $45.1 million as compared to approximately $37.2 million as of December 31, 2002. This backlog consists of direct customer and distributor orders scheduled for delivery within the next 90 days. Distributor orders accounted for the majority of the backlog in both periods. Direct customer orders may be changed, rescheduled or cancelled under certain circumstances without penalty prior to

7

shipment. Additionally, distributor orders generally may be changed, rescheduled or cancelled without penalty prior to shipment. Furthermore, distributor shipments are subject to rights of return and price adjustment. Revenue associated with distributor shipments is not recognized until the product is resold to an end customer. Typically, the majority of our revenue results from orders placed and filled within the same period. Such orders are referred to as "turns orders." By definition, turns orders are not captured in a backlog measurement made at the beginning of a period. We do not anticipate a significant change in this business pattern. For all these reasons, backlog as of any particular date should not be used as a predictor of revenue for any future period.

Competition

        The semiconductor industry is intensely competitive and characterized by rapid rates of technological change, product obsolescence and price erosion. Our current and potential competitors include a broad range of semiconductor companies from emerging companies to large, established companies, many of which have greater financial, technical, manufacturing, marketing and sales resources than we do.

        The principal competitive factors in the PLD market include product features, price, customer support, and sales, marketing and distribution strength. The availability of competitive software development tools is also critical. In addition to product features such as density, speed, power consumption, reprogrammability, design flexibility and reliability, competition in the PLD market occurs on the basis of price and market acceptance of specific products and technology. We believe that we compete favorably with respect to each of these factors. We intend to continue to address these competitive factors by working to continually introduce product enhancements and new products, by seeking to establish our products as industry standards in their respective markets, and by working to reduce the manufacturing cost of our products.

        In the PLD market, we directly compete with Actel Corporation, Altera Corporation and Xilinx Inc., all of whom offer competing products. We also indirectly compete with other semiconductor companies who provide non-PLD based logic solutions. Although to date we have not experienced significant competition from companies located outside the United States, such companies may become a more significant competitive factor in the future. Competition may also increase if other semiconductor companies seek to expand into our market. Any such increases in competition could have a material adverse effect on our operating results.

Patents

        We seek to protect our products and wafer fabrication process technologies primarily through patents, trade secrecy measures, copyrights, mask work protection, trademark registrations, licensing restrictions, confidentiality agreements and other approaches designed to protect proprietary information. There can be no assurance that others may not independently develop competitive technology not covered by our intellectual property rights or that measures we take to protect our technology will be effective.

        We hold numerous domestic, European and Asian patents and have patent applications pending in the United States, Asia and Europe. Our current patents will expire at various times between 2004 and 2022. There can be no assurance that pending patent applications or other applications that may be filed will result in issued patents, or that any issued patents will survive challenges to their validity. Although we believe that our patents have value, there can be no assurance that our patents, or any additional patents that may be issued in the future, will provide meaningful protection from competition. We believe that our success will depend primarily upon the technical expertise, experience, creativity and the sales and marketing abilities of our personnel.

8

        Patent and other proprietary rights infringement claims are common in our industry. There can be no assurance that, with respect to any claim made against us, we could obtain a license on terms or under conditions that would not harm our business.

Licenses and Agreements

Advanced Micro Devices

        In 1999, as part of our acquisition of Vantis Corporation, a wholly-owned subsidiary of Advanced Micro Devices, Inc. ("AMD"), we entered into an agreement with AMD pursuant to which we have cross-licensed Vantis patents with AMD patents, having an effective filing date on or before June 15, 1999, related to PLD products. This cross-license was made on a worldwide, non-exclusive and royalty-free basis.

        Additionally, as part of our acquisition of Vantis, we acquired certain third-party license rights held by Vantis prior to the acquisition. Included are rights to use certain Xilinx patents to manufacture, market and sell products.

Agere Systems

        In 2002, as part of our acquisition of the FPGA business of Agere, we entered into an intellectual property agreement with Agere and Agere Systems Guardian Corporation. Pursuant to this agreement, these Agere companies assigned or licensed to us certain FPGA and FPSC patents, trademarks, software and other intellectual property rights and technology, and we licensed back rights in these same assets. These cross-licenses were made on a worldwide and royalty-free basis.

Altera

        In 2001, we entered into a comprehensive, royalty-free patent cross-license agreement and a multi-year patent peace agreement with Altera.

Chartered Semiconductor

        In 2002, in order to support our acquired and subsequently developed ORCA FPGA products, Chartered Semiconductor and its affiliates agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts. We have agreed to make a portion of the rolling forecasts non-cancellable. Prices for the wafers obtained are reviewed and adjusted periodically. Wafers for our products are manufactured at the facilities of Chartered and its affiliates in Singapore.

Fujitsu

        In March 2004, we announced that Fujitsu Limited has agreed to manufacture our next generation FPGA products on its 130 nanometer and 90 nanometer CMOS process technologies, as well as on a 130 nanometer technology with embedded Flash memory that we are jointly developing with Fujitsu. Additionally, in an effort to secure a long-term, stable advanced technology wafer supply, we plan to invest between $100 million and $200 million in Fujitsu's planned new 300mm wafer fab. Presently, we contemplate making this investment in stages before the end of 2005 and structuring the investment as an advance payment for production wafers and for access to future process technologies. The detailed terms of the investment are not yet finalized.

Seiko Epson/Epson Electronics America

        Epson Electronics America ("EEA"), an affiliated U.S. distributor of Seiko Epson, has agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts. We have agreed to make a portion of the rolling forecasts non-cancellable. Prices for the wafers obtained from EEA are

9

reviewed and adjusted periodically. Wafers for our products are manufactured in Japan at Seiko Epson's wafer fabrication facilities and are delivered to us by EEA.

        In 1997, and as subsequently amended in January 2002, we entered into an advance production payment agreement with Seiko Epson and EEA under which we agreed to advance up to approximately $69 million, payable upon completion of specific milestones, to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility. The timing of the payments is related to certain milestones in the development of the facility. Under the terms of the agreement, the advance is to be repaid with semiconductor wafers over a multi-year period. The agreement calls for wafers to be supplied by Seiko Epson through EEA pursuant to purchase agreements concluded with EEA. Payments of approximately $51.3 million have been made under this agreement. Cumulatively, approximately $15.6 million of these payments have been repaid to us in the form of semiconductor wafers. We do not anticipate making additional payments under this agreement.

UMC Group

        Beginning in 1995, we entered into a series of agreements with UMC pursuant to which we agreed to make several equity investments in entities now directly owned by UMC. Under the terms of these agreements, we invested approximately $68.5 million for the right to purchase a percentage of UMC's wafer production at market prices.

        As of December 31, 2003, we owned 91.7 million shares of UMC of which 23.3 million were restricted from sale for more than one year by the terms of our agreements with UMC. Under the terms of our agreements, if we sell any of these restricted shares, our rights to guaranteed wafer capacity at UMC may be reduced on a pro-rata basis based on the number of shares that we sell. If we sell over 10.1 million of these restricted shares, we may lose all of our rights to guaranteed wafer capacity at UMC.

        In the first quarter of 2004, we sold 10.0 million of our unrestricted UMC shares for approximately $9.2 million in cash, resulting in a gain of approximately $2.5 million. This gain will be reflected in Other Income, net, in our consolidated financial statements for the quarter ended March 31, 2004.

Employees

        As of December 31, 2003 we had 1,048 full-time employees. We believe that our future success will depend, in part, on our ability to continue to attract and retain highly skilled technical and management personnel. None of our employees is subject to a collective bargaining agreement. We have never experienced a work stoppage and consider our employee relations to be good.

10

EXECUTIVE OFFICERS AND DIRECTORS OF THE REGISTRANT

        The following individuals currently serve as our executive officers and directors:

        Cyrus Y. Tsui joined Lattice in September 1988 as President and Chief Executive Officer and in March 1991 was named Chairman of the Board. From 1987 until he joined Lattice, Mr. Tsui was Corporate Vice President and General Manager of the Programmable Logic Division of AMD. He was Vice President and General Manager of the Commercial Products Divisions of Monolithic Memories Incorporated (MMI) from 1983 until its merger with AMD in 1987. Mr. Tsui has held technical and managerial positions in the semiconductor industry for over 30 years and worked in the programmable logic industry since its inception.

        Stephen A. Skaggs joined Lattice in December 1992 as Director, Corporate Development. He was elected Senior Vice President, Chief Financial Officer and Secretary in August 1996. In October 2003 he was elected President.

        Jan Johannessen rejoined Lattice in October 2001 as Vice President, Investments. In October 2003, he was elected Corporate Vice President and Chief Financial Officer. He originally joined Lattice in 1983 and served as Vice President and Chief Financial Officer between 1987 and 1993. From 1993 to 2001 he worked as an independent venture capitalist.

        Frank J. Barone joined Lattice in June 1999 as a Corporate Vice President as a result of our Vantis acquisition. From September 1997 until he joined our company, Mr. Barone was Chief Operating Officer of Vantis. Prior thereto, Mr. Barone held various technical and managerial positions at AMD. He has worked in the programmable logic industry since 1978.

        Stephen M. Donovan joined Lattice in October 1989 and has served as Director of Marketing and Director of International Sales. He was elected Vice President, International Sales in August 1993. He was promoted to Corporate Vice President, Sales, in May 1998. Mr. Donovan has worked in the programmable logic industry since 1982.

        Jonathan K. Yu joined Lattice in February 1992 as Vice President, Operations. He was elected Corporate Vice President, Business Development in August 1996. Mr. Yu has held technical and managerial positions in the semiconductor industry for over 30 years.

        Martin R. Baker joined Lattice in January 1997 as Vice President and General Counsel. From 1991 until he joined Lattice, Mr. Baker held legal positions with Altera Corporation.

        Rodney F. Sloss joined Lattice in May 1994 as Vice President, Finance.

11

        Mark O. Hatfield has been a member of our board of directors since 1997. Mr. Hatfield is a former U.S. Senator from Oregon, a position he held until January 1997. He has served as a Distinguished Professor at Portland State University since 1997, a Distinguished Professor at George Fox University since 1997 and an Adjunct Professor at Lewis & Clark College since 2000.

        Daniel S. Hauer has been a member of our board of directors since 1987. Mr. Hauer served as the Chairman of the Board and Chief Executive Officer of Epson Electronics America until November 1998. Since that time, Mr. Hauer has worked as a business consultant.

        Soo Boon Koh joined our board of directors in August 2000. Ms. Koh has served as Managing Partner of iGlobe Partners Fund, L.P., a venture capital firm located in Singapore and the United States, since October 1999. She previously served as Sr. Vice President and Deputy General Manager of Vertex Management Pte, Ltd. until June 1999.

        Harry A. Merlo was a founding member of our board of directors in 1983. Mr. Merlo has been the President of Merlo Corporation since July 1995. He previously served as the founding President and Chairman of the Board of Louisiana-Pacific Corporation until June 1995.

        Larry W. Sonsini has been a member of our board of directors since 1991. Mr. Sonsini is a member of Wilson Sonsini Goodrich & Rosati, Professional Corporation, a law firm, and Chairman of the firm's Executive Management Committee. He also serves on the board of directors of Brocade Communications Systems, Inc., Echelon Corporation, LSI Logic Corporation, Pixar, Inc. and Silicon Valley Bancshares.

Available Information

        We make available free of charge through our website at www.latticesemi.com, via a link to the SEC's website at www.sec.gov, our annual reports on Form 10-K, quarterly reports on Form 10-Q and current reports on Form 8-K and amendments to those reports as soon as reasonably practicable after such materials are electronically filed with, or furnished to, the SEC. You may also obtain free copies of these materials by contacting our Investor Relations Department at 5555 N.E. Moore Court, Hillsboro, Oregon 97124-6421, telephone (503) 268-8000.

Item 2. Properties.

        Our corporate headquarters consists of land and 200,000 square feet of buildings we own in Hillsboro, Oregon. We also own two research and development facilities totaling 29,000 square feet and approximately 6,000 square feet of dormitory facilities in Shanghai, China. We lease a 133,000 square foot research and development facility in San Jose, California through 2008; a 25,000 square foot research and development facility in Austin, Texas through 2011; and a 7,500 square foot research and development facility in the United Kingdom through 2013. We also lease, on a short-term basis, research and development facilities in Colorado, Illinois, Pennsylvania and Utah, and office facilities in multiple metropolitan locations for our domestic and international sales staff. Additionally, we lease (through 2006) an 80,000 square foot facility in Sunnyvale, California which has been subleased to a third party through the end of the lease term. We believe that our existing facilities are adequate for our current and foreseeable future needs.

Item 3. Legal Proceedings.

        We are not currently a party to any material legal proceedings.

Item 4. Submission of Matters to a Vote of Security Holders.

        Not applicable.

12

PART II

Item 5. Market for the Registrant's Common Stock and Related Stockholder Matters.

        Our common stock is traded on the over-the-counter market and prices are quoted on the Nasdaq National Market under the symbol "LSCC." The following table sets forth the low and high sale prices for our common stock for the last two fiscal years, as reported by the Nasdaq National Market. As of March 29, 2004, we had approximately 484 stockholders of record.

        The payment of dividends on our common stock is within the discretion of our Board of Directors. We intend to retain earnings to finance the growth of our business. We have never paid cash dividends.

Recent Sales of Unregistered Securities

        On May 6, 2003, we issued a warrant to purchase 256,661 shares of our common stock to Bain & Company, Inc., in connection with consulting services provided to us. The warrant has an exercise price of $9.05 per share, and vests at a rate of 21,388.42 shares on the first day of each month, beginning March 1, 2003, subject to Bain's continued service as a consultant to us. The foregoing transaction was exempt from registration under the Securities Act of 1933, as amended, pursuant to Section 4(2) thereof.

        On June 20, 2003, we sold $200 million in principal amount of our Zero Coupon Convertible Subordinated Notes due July 1, 2010 to Goldman Sachs & Co., the initial purchaser, for $195.0 million pursuant to the exemption from registration under Section 4(2) of the Securities Act of 1933, as amended, for resale by the initial purchaser to qualified institutional buyers pursuant to Rule 144A under the Securities Act of 1933, as amended. Holders of these notes may convert the notes into shares of our common stock at any time before the close of business on the date of their maturity, unless the notes have been previously redeemed or repurchased, if (1) the price of our common stock issuable upon conversion of a note reaches a specified threshold, (2) the notes are called for redemption, (3) specified corporate transactions occur or (4) the trading price of the notes falls below certain thresholds. The conversion price is approximately $12.06 per share, subject to adjustment in certain circumstances. On or after July 1, 2008, we have the option to redeem all or a portion of the notes that have not been previously repurchased or converted at 100% of the principal amount of the notes. On July 1, 2008, holders have the option to require us to purchase all or a portion of their notes in cash at 100% of the principal amount of the notes. Holders also have the right, subject to certain conditions, to require us to repurchase the notes in the event of a "fundamental change" (as defined in the indenture governing the notes) at 100% of the principal amount of the notes.

13

Item 6. Selected Financial Data.

(1)

Includes $5,745, $2,962 and $397 of amortization of deferred stock compensation expense for the years ended December 31, 2003, December 31, 2002 and December 31, 2001, respectively, attributable to research and development activities.

        All share and per share amounts have been adjusted retroactively to reflect two-for-one stock splits effected in the form of stock dividends and paid on October 11, 2000 and September 16, 1999.

14

Unaudited Quarterly Data

(1)

In January 2004, management learned of certain incorrect accounting entries relating to our deferred income accounting for sales to distributors in the quarters ended June 30, 2003 and September 30, 2003. Pursuant to our accounting principles for revenue recognition, we defer reporting revenue from sales to distributors until the period in which the distributors resell our product to their customers. The Audit Committee of our Board of Directors undertook an investigation of this matter with the assistance of our independent auditor and outside legal counsel. That investigation is complete and the Audit Committee has recommended the adoption of certain internal control and system enhancements. We are currently implementing these Audit Committee directives. As a result of the investigation, we have determined that entries made in the second and third quarters of 2003 which reduced Accrued Expenses in the amount of $1.3 million and $4.2 million, respectively, were inappropriate. We also determined that our systems, procedures and controls surrounding (1) our estimation of resales by our distributors and (2) our determination of deferred revenue related to distributor inventories needed to be improved. During the investigation, we carried out additional procedures to (1) refine our estimate of the amount of distributor resale revenue and (2) refine our method for estimating deferred revenue related to distributor inventories. As a result of those additional procedures, we believe our Consolidated Balance Sheet Deferred Income account was understated at March 31, 2003, June&nb