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UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549

FORM 10-K

OR

For the transition period from                              to                             

Commission File Number: 000-22671

QUICKLOGIC CORPORATION
(Exact name of registrant as specified in its charter)

1277 Orleans Drive
Sunnyvale, CA 94089
(Address of principal executive offices, including zip code)

Registrant's telephone number, including area code: (408) 990-4000

Securities registered pursuant to Section 12(b) of the Act: None

Securities registered pursuant to Section 12(g) of the Act: Common Stock, $0.001 par value

(Title of Class)

        Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes ý  No o

        Indicate by check mark if disclosure of delinquent filers pursuant to item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. ý

        Indicate by check mark whether the registrant is an accelerated filer (as defined in Rule 12b-2 of the Act). o

        The aggregate market value of voting stock held by non-affiliates of the registrant as of March 7, 2003 was $22,968,891 based upon the last sales price reported for such date on The Nasdaq National Market. For purposes of this disclosure, shares of common stock held by persons who hold more than 5% of the outstanding shares of common stock and shares held by executive officers and directors of the registrant have been excluded in that such persons may be deemed to be affiliates. This determination is not necessarily conclusive.

        At March 7, 2003 Registrant had outstanding 23,758,578 shares of common stock.

DOCUMENTS INCORPORATED BY REFERENCE

        The Registrant has incorporated by reference into Part III of this Form 10-K portions of its Proxy Statement for Registrant's Annual Meeting of Stockholders to be held on or about April 22, 2003.

EXPLANATORY NOTE

        Statements in this Business section, and elsewhere in this Annual Report on Form 10-K, which express that QuickLogic "believes," "anticipates" or "plans to....," as well as other statements which are not historical fact, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Actual events or results may differ materially as a result of the risks and uncertainties described herein and elsewhere including, in particular, those factors described under "Management's Discussion and Analysis of Financial Condition and Results of Operations" and "Risk Factors."

PART I

ITEM 1. BUSINESS

Overview

        QuickLogic Corporation develops, markets and supports advanced Field Programmable Gate Array, or FPGA, and Embedded Standard Product, or ESP, semiconductors and the software tools that enable design engineers to use our products. We introduced ESPs, a new class of semiconductor devices, in 1998, to address the design community's demand for a solution that provides a powerful alternative to the existing options: Application Specific Integrated Circuits, or ASICs, and the long-sought-after system-on-a-chip products. Specifically, our ESP devices provide engineers with the ease-of-use, guaranteed functionality and high performance of standard products, such as ASICs, combined with the flexibility of programmable logic. Our ESP and FPGA products target complex, high-performance systems in rapidly changing markets where system manufacturers seek to minimize time-to-market and maximize product differentiation and functionality. We compete in various markets, including: high-performance computing; instrumentation and test; data communications and telecommunications; video/audio and graphics imaging; and military and aerospace systems.

        In August 2001, we acquired certain assets of V3 Semiconductor, Inc., a manufacturer of application specific standard products, or ASSPs. The acquisition of V3 provided us with an ASSP design center in Canada and with ASSP products that complement our ESP products.

        QuickLogic was incorporated in California in 1988 and reincorporated in Delaware in 1999. Our headquarters are located at 1277 Orleans Drive, Sunnyvale, California 94089. We can be reached at (408) 990-4000, and our website address is www.quicklogic.com.

Product Technology

        The key components of our ESP and FPGA product families are our ViaLink® programmable metal technology, our user-programmable platform and the associated software tools used for system design. Our ViaLink technology allows us to create devices smaller than competitors' comparable products, thereby minimizing silicon area and cost. In addition, our ViaLink technology has lower electrical resistance and capacitance than other programmable technologies and, consequently, supports higher signal-speed and low power consumption. Our user-programmable platform facilitates full utilization of a device's logic cells, clocks and Input/Output pins. These logic cells have been optimized to efficiently implement a wide range of logic functions at high speed, thereby enabling greater usable device density and design flexibility. Our architecture uses our ViaLink technology to maximize interconnects at every routing wire intersection. The abundance of interconnect resources allows more paths between logic cells. As a consequence, system designers are able to use QuickLogic devices with smaller gate counts than competing FPGAs to implement their designs. These smaller gate-count devices require less silicon area and as a result are able to be offered at a lower price. ViaLink offers intellectual property security to our customers, since it is difficult to reverse engineer intellectual property that is implemented using our one-time-programmable ViaLink technology. Finally, our software enables our customers to efficiently implement their designs using our products.

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Industry Background

        Competitive pressures are forcing manufacturers of electronic systems to rapidly bring to market products with improved functionality, higher performance and greater reliability, all at lower cost. Providers of systems requiring high-speed data transmission and processing such as computing equipment, storage sub-systems, instrumentation and test equipment, communications equipment, and digital image products face intense time-to-market pressures. These market forces have driven the evolution of logic semiconductors, which are used in complex electronic systems to coordinate the functions of other semiconductors, such as microprocessors or memory. There are three types of advanced logic semiconductors:

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Application specific integrated circuits, or ASICs, are special purpose devices designed for a particular manufacturer's electronic system. These devices are customized during wafer manufacturing;



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Application specific standard products, or ASSPs, are fixed-function devices designed to comply with industry standards that can be used by a variety of electronic systems manufacturers. Their functions are fixed prior to wafer fabrication; and



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Programmable logic devices, or PLDs, are general-purpose devices, which can be used by a variety of electronic systems manufacturers, and are customized after purchase for a specific application. Field programmable gate arrays, or FPGAs, are types of PLDs used for complex functions.

        Systems manufacturers have relied heavily on ASICs to implement the advanced logic required for their products. ASICs provide high performance due to customized circuit design. However, because ASICs are design-specific devices, they require long development and manufacturing cycles, delaying product introductions. In addition, because of the expense associated with the design of ASICs, they are cost effective only if they can be manufactured in high volumes. Finally, once ASICs are manufactured, their functionality cannot typically be changed to respond to evolving market demands.

        ASSPs have become widely utilized, as industry standards have developed to address increasing system complexity and the need for communication between systems and system components. These standards include:

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Peripheral component interconnect, or PCI, a standard developed to provide a high performance, reliable and cost-effective method of connecting high-speed devices within a system;



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Synchronous optical network, or SONET, a fiber-optic transmission standard for high-speed digital traffic, employed mainly by telephone companies and other network service providers;



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Ethernet, a widely-used local area network, or LAN, transport standard which controls the interconnection between servers and computers; and



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Fibre channel interconnect protocol, an industry-networking standard for storage area networks, or SANs, which controls the interconnection between servers and storage devices.

        Compared to ASICs, ASSPs offer the systems designer shorter development time, proven functionality, lower risk and reduced development cost. However, ASSPs generally cannot be used by systems manufacturers to differentiate their products. To address markets where industry standards do not exist or are changing and time-to-market is important, PLDs are often used. These products provide systems manufacturers with the flexibility to customize and thereby differentiate their systems, unlike ASSPs. PLDs also enable systems manufacturers to change the logic functionality of their systems after product introduction without the expense and time of redesigning an ASIC. However, most PLDs are more expensive than ASSPs and even ASICs of equivalent functionality because they

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require more silicon area. In addition, most PLDs offer lower performance than non-programmable solutions, such as ASSPs and ASICs.

Industry Future: System-on-a-Chip

        Over the past few years, semiconductor manufacturers have migrated to smaller process geometries. These smaller process geometries enable more logic elements to be incorporated in a single chip using less silicon area. More recently, advances have been made in the integration of logic and memory on a single chip, which had been difficult previously due to incompatible process technologies. The industry "holy grail" is to have the three basic components of electronic circuit boards; logic, memory and a microprocessor, on the same chip. Advantages of the single-chip approach to systems manufacturers include:

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simplified system development;



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reduced time-to-market;



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elimination of delays associated with the transfer of data between chips;



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smaller physical size;



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lower power dissipation;



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greater reliability; and



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lower cost.

        However, as levels of logic integration have increased, devices have become more specific to a particular application. This fact limits their use and potential customer base. At this point in time, the potential of system-on-a-chip is compelling. However, the benefits of higher performance, low form factors, and low unit costs are quickly offset by high non-recurring engineering charges, expensive development and tool costs, long development cycles, and issues associated with intellectual property. Instead of banking on a risky system-on-a-chip alternative, many designers rely on traditional FPGA or ASIC solutions. This approach often requires using large, expensive devices—or even multiple devices—and typically requires extensive development time to implement.

QuickLogic's ESP Solution

        QuickLogic has leveraged its unique ViaLink technology and user-programmable platform to address the limitations inherent in current system-on-a-chip approaches. The result is Embedded Standard Products, or ESPs, that deliver the advantages offered by both FPGAs and ASSPs. In its simplest form, an ESP contains three basic parts: a programmable logic array, an embedded standard function, and a flexible interface that allows communication between the standard function and programmable logic array. Our ESP products combine the system-level functionality of ASSPs with the flexibility of FPGAs. We believe ESPs offer the following specific advantages:

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Increased Performance. In a typical design, data must travel between an ASSP and an FPGA across a printed circuit board. The limited number of connections available and the distance between the devices can degrade the system's overall performance. Our ESP solution allows all data to be processed on a single chip;



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Decreased Cost. Because our ESP is a single chip solution, it requires less silicon area, and therefore is less expensive to produce. Additionally, this single chip approach lowers the component, assembly and test cost for the system manufacturer;



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Increased Reliability. ESP designs are more reliable because single chip solutions contain fewer components and circuit board connections that are subject to failure; and

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Shorter Development Time. With a multiple chip design, systems designers must solve complex routing and timing issues between devices. A single chip ESP provides an "out-of-the-box" solution to the timing issues between devices and simplifies software simulation, leading to shorter development time.

        QuickLogic's QuickMIPS family was introduced in 2001. This product is truly a "programmable system-on-a-chip" and best represents the benefits that designers can realize using our ESP technology. The current product development cycle is generally sequential—hardware is developed first, followed by software, and finally system integration and testing. If the systems architect (who typically manages all these functions) needs to make hardware/software trade-offs, a prototype board must be developed. This can extend development time and increase costs. Designers using QuickMIPS can develop software and hardware in parallel—cutting development time and reducing total cost of ownership.

        The QuickMIPS family is a complete solution. All elements needed to develop an electronics system are included—a device (which contains flexible programmable logic and a high-performance MIPS processor core), a prototype or development board, a complete set of development tools, and popular features (buses, ethernet MACs, PCI, UARTs, etc.) that enable the QuickMIPS device to communicate with other components on the board. Finally, because these devices are based on our ViaLink technology, the design is secure and therefore the design investment is secure as well.

        Many of today's embedded electronic systems require peripheral component interconnect, or PCI, bridging capabilities. Often large and complex, these designs can require the developer to become a PCI "expert" in real time—time that is often not available. QuickLogic's QuickPCI family provides a range of PCI bridging solutions, all of which are based on our ViaLink technology. Because our QuickPCI products are complete solutions—they include a device, comprehensive software and hardware development kits, and a variety of development services—they allow the PCI interface to be implemented quickly and easily. Therefore, the designer spends less time architecting the PCI interface and the resulting production cycle is shorter. In addition, the designer can focus on adding value to the end product by using his or her expertise on other areas of the design.

        Our QuickRAM family serves applications that require embedded memory. Our ESP families are designed for performance-driven applications. QuickLogic has introduced several other ESP products. ESP development efforts during 2002 were focused on expanding our PCI product line and designing QuickMIPS products using advanced wafer manufacturing technology.

QuickLogic's FPGA Solution

        QuickLogic's FPGAs offer high performance at low power and competitive pricing when compared to alternative FPGA solutions, in addition to offering the advantages typically associated with FPGAs. Specifically, our products provide greater design flexibility than standard FPGAs and enable designers of complex systems to achieve rapid time-to-market with highly differentiated products. Our products are based on our ViaLink technology and user-programmable platform, and our associated QuickWorks and QuickTools design software.

        During 2000, we introduced a new FPGA family called Eclipse—devices that offer a host of new system-level features that are ideal for computing and test, telecommunications and networking applications that require a combination of high-performance, high density and embedded random access memory, or RAM. In addition, we continue to sell our three families of pASIC FPGAs. FPGA development efforts during 2002 were focused on developing an advanced wafer manufacturing technology, which will allow us to expand our product lines and offer higher value to our customers.

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The QuickLogic Strategy

        Our objective is to be the indispensable provider of high-speed, flexible, cost-effective ESPs—products that integrate standard functions and programmable logic. We believe ESPs offer systems manufacturers the ability to accelerate design cycles to satisfy demanding time-to-market requirements while reducing their total cost of ownership. To achieve our objective, we have adopted the following strategies:

Extend Technology Leadership

        Our ViaLink technology, FPGA architecture, ASSP design capabilities, user-programmable platform and proprietary software design tools enable us to offer flexible, high-performance ESP products. We intend to continue to invest in the development of these technologies and to utilize such developments in future innovations of our ESP products. We also intend to focus engineering resources on developing systems-level ESP solutions. We target applications that benefit from the flexibility of programmable logic, including:

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programmable system-on-a-chip applications;



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interconnect applications such as PCI bridging;



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low power, volume applications typically reserved for ASICs; and



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applications that are difficult or expensive to implement in traditional FPGAs.

        Specifically, we intend to focus our design and marketing efforts on systems manufacturers who sell complex systems within our target market segments. These include:

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high-performance computing;



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instrumentation and test;



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data communications and telecommunications;



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video/audio and graphics and imaging; and



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military and aerospace systems.

Provide Complete System Solutions

        Our focus on a more targeted set of applications and market segments allows us to provide value-added solutions to systems manufacturers. These solutions include not only the device and design software, but also software drivers, reference designs, test boards and complementary intellectual property functions. We currently focus ESP development efforts on two strategic applications areas:

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embedded high-performance processing solutions; and



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embedded PCI bridging solutions.

Strategic Alliances

        As a part of our ESP strategy, we have engaged with MIPS Technologies, Tower Semiconductor, Aeroflex UTMC Microelectronics Systems, Inc., and other companies to expand the range of technology that we embed in our products. In addition, we continue to sell through a network of industry sales representatives and distributors. These alliances are an essential element of our ESP strategy and a source of competitive strength going forward. By leveraging the expertise of our partners in intellectual property development, wafer fabrication and sales, we can devote our effort to the development of targeted, well-defined ESP products.

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Create Innovative, Industry-Leading Customer Services

        We continue to develop and implement innovative ways to serve and communicate with our customers. For example, our WebASIC service allows customers to use our development software to design a circuit, transmit design information over the Internet and receive a QuickLogic ESP or FPGA device programmed with their design within one business day in North America and Europe or within two business days in Asia. In addition, our ProChannel web-based system allows our distributors to receive quotations, place orders for our products and view their order status over the Internet. This system complements the Electronic Data Interchange systems that we have used for the past several years with our largest customers.

        We have recently added MyDesign.com as an innovative way to serve and communicate with customers. MyDesign is a secure design-support portal individualized for each of our customers. It provides us with the ability to exchange information and advance system designs using our ESP and FPGA products.

Customers and Markets

        The following chart provides a representative list by industry of our current customers and the markets in which they do business:

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Sales and Technical Support

        We sell our products through a network of sales managers, independent sales representatives and electronics distributors in North America, Europe and Asia. In addition to our corporate headquarters in Sunnyvale, we have regional sales operations in Los Angeles, Dallas, Minneapolis, Boston, Raleigh, London, Munich, Shin-Yokohama, Shanghai and Hong Kong. Our sales personnel and independent sales representatives are responsible for sales and applications support for a given region of responsibility. Our sales managers and independent sales representatives generally focus on major strategic accounts. Our distributor partnerships generally focus on customers who are not directly served by our sales managers.

        Currently in North America, our distributors include the Cilicon group of Avnet. Inc., and Future Electronics. A network of distributors throughout Europe and Asia supports our international business. These firms work with our regional sales managers in discovering new opportunities, satisfying customer needs, providing technical support and other value-added services. This activity takes place with new customers as well as existing customers. From time-to-time, we add or delete distributors and sales representatives, as appropriate to meet our needs.

        We provide systems manufacturers with comprehensive technical support, which we believe is critical to remaining competitive in the markets we serve. Our factory-based and distributor applications support organizations provide pre-sales and on-site technical support to customers.

Competition

        The semiconductor industry is intensely competitive and is characterized by constant technological change, rapid rates of product obsolescence and price erosion. A number of companies offer products that compete with one or more of our products. Our existing competitors include suppliers of conventional standard products, such as PLX Technology; suppliers of complex programmable logic devices, or CPLDs, including Lattice Semiconductor and Altera; suppliers of FPGAs, particularly Xilinx and Actel; and suppliers of embedded processors, such as Integrated Device Technology and Motorola. Xilinx and Altera dominate the programmable logic market and have substantially greater revenue, market presence and financial resources, than Actel, Lattice or us. Xilinx dominates the FPGA segment of the market while Altera dominates the CPLD segment of the market. We also face competition from companies that offer gate arrays, which can be obtained at a lower cost for high volumes and may have gate densities and performance equal or superior to our products. As we introduce additional ESPs, we will also face competition from standard product manufacturers who are already servicing or who may decide to enter the markets addressed by these ESP devices. In addition, we expect significant competition in the future from major domestic and international semiconductor suppliers. We also may face competition from suppliers of products based on new or emerging technologies. Increased competition is likely to result in price reductions, reduced gross margins and loss of market share, any one of which could seriously harm our business.

        We believe that important competitive factors in our market are length of development cycle, price, performance, installed base of development systems, adaptability of products to specific applications, ease of use and functionality of development system software, reliability, technical service and support, wafer fabrication capacity and sources of raw materials, market presence, financial strength and protection of products by effective utilization of intellectual property laws.

Research and Development

        Our future success will depend to a large extent on our ability to rapidly develop and introduce new products and enhancements to our existing products that meet emerging industry standards and satisfy changing customer requirements. We have made and expect to continue to make substantial

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investments in research and development and to participate in the development of new and existing industry standards.

        As of December 31, 2002, our research and development staff consisted of 57 employees working in three locations: Canada, India and Sunnyvale. The Canadian group specializes in system level issues, and has responsibility for the physical design of the ASSP portion of our ESP products, and for the operating system and tool flow support of our MIPS based products. The Indian group specializes in the EDA tools required to support the programmable fabric that is used in both our ESP products and our FPGA products. The Sunnyvale groups support the physical design of the programmable fabric-process, logic design, and programming—as well as developing mixed-signal blocks, and certain portions of the EDA tools required to support the programmable fabric.

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Our process engineering group develops our proprietary ViaLink wafer manufacturing process, oversees product manufacturing and process development with our third-party foundries, and is involved in ongoing process improvements to increase yields and optimize device characteristics.



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Our mixed-signal engineering group develops high-performance analog circuits to support our ESP products.



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Our FPGA design engineering group develops high-performance programmable systems that can be used stand-alone or combined with high value dedicated functions to form ESP products.



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Our ASSP design engineering group develops or integrates dedicated IP functions that are combined with a programmable system to produce ESP products.



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Our FPGA software group develops the design libraries, interface routines and place and route software that allows our customers to use third-party design environments to develop designs for our programmable systems and subsystems.



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Our embedded systems group develops the software required to program and use our MIPS based products.

        Our research and development expenses for 2000, 2001 and 2002 were $9.3 million, $14.3 million and $13.1 million, respectively. The increase in research and development expenses is primarily due to increased ESP development activity. We anticipate that we will continue to commit substantial resources to research and development in the future.

Manufacturing

        We have established close relationships with third-party manufacturers for our wafer fabrication, package assembly, test and programming requirements in an effort to ensure stability in the supply of our products and minimize the risk of localized capacity constraints.

        We currently outsource all of our wafer manufacturing to Cypress Semiconductor Corporation, at its Round Rock, Texas facility; to Taiwan Semiconductor Manufacturing Company, or TSMC, at its Taiwan facilities; and to Samsung Semiconductor, Inc. Cypress manufactures our pASIC1 and pASIC2 product families using a three-layer metal, 0.65 micron CMOS process on six-inch wafers. TSMC manufactures our pASIC3, QuickRAM and QuickPCI product families using a four-layer metal, 0.35 micron CMOS process. TSMC also manufactures our Eclipse and other ESP products using a five-layer metal, 0.25 micron process on eight-inch wafers. Samsung manufactures certain QuickPCI products. Our Cypress agreement provides a guaranteed capacity availability. We purchase products from TSMC and Samsung on a purchase order basis.

        On December 12, 2000 we entered into a Share Purchase Agreement, a Foundry Agreement and other related agreements with Tower Semiconductor Ltd., under which we agreed to make a $25 million strategic investment in Tower as part of Tower's plan to build and equip a new wafer

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fabrication facility. The new fabrication facility is expected to produce 200-mm wafers in geometries of 0.18 micron and below, using advanced CMOS technology from Toshiba. Tower has agreed to develop manufacturing capability for our proprietary ViaLink technology, and supply us with a guaranteed portion of the new fabrication facility's available wafer capacity at competitive pricing, with first production expected in 2003.

        We outsource our product packaging, test and programming to Amkor Technology and ChipPAC, Inc. at their South Korea facilities and to Advanced Semiconductor Engineering, or ASE, at its Taiwan facility, among others.

Employees

        As of December 31, 2002, we had a total of 157 employees worldwide, with 33 employees in operations, 57 employees in research and development, 22 employees in sales, 19 employees in marketing and 26 employees in administration. We believe that our future success will depend in part on our continued ability to attract, hire and retain qualified personnel. Since September 2002 we have significantly reduced our workforce to better align expenses with gross profit levels. None of our employees is represented by a labor union, and we believe our employee relations are favorable.

Intellectual Property

        Our future success and competitive position depend upon our ability to obtain and maintain the proprietary technology used in our principal products. We hold 90 U.S. patents and have 3 pending applications for additional U.S. patents containing claims covering various aspects of programmable integrated circuits, programmable interconnect structures and programmable metal devices. Additionally in Japan, we have two patent applications pending and three granted. In Europe, we have two patent applications pending and in Korea we have two patent applications pending. Our issued patents expire between 2009 and 2019. We have also registered seven trademarks with the U.S. Patent and Trademark Office.

        Because it is critical to our success that we are able to prevent competitors from copying our innovations, we intend to continue to seek patent protection for our products. The process of seeking patent protection can be long and expensive, and we cannot be certain that any currently pending or future applications will actually result in issued patents, or that, even if patents are issued, they will be of sufficient scope or strength to provide meaningful protection or any commercial advantage to us. Furthermore, others may develop technologies that are similar or superior to our technology or design around the patents we own.

        We also rely on trade secret protection for our technology, in part through confidentiality agreements with our employees, consultants and third parties. However, employees may breach these agreements, and we may not have adequate remedies for any breach. In any case, others may come to know about or determine our trade secrets through a variety of methods. In addition, the laws of certain territories in which we develop, manufacture or sell our products may not protect our intellectual property rights to the same extent as do the laws of the United States.

        From time to time, we receive letters alleging patent infringement or inviting us to take a license to other parties' patents. We evaluate these letters on a case-by-case basis. Offers such as these may lead to litigation if we reject the opportunity to obtain the license.

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Executive Officers and Directors

        The following table sets forth certain information concerning our current executive officers and directors as of March 7, 2003:

        E. Thomas Hart has served as our President, Chief Executive Officer and a member of our board of directors since June 1994, and as our Chairman since April 2001. Prior to joining QuickLogic, Mr. Hart was Vice President and General Manager of the Advanced Networks Division at National Semiconductor, a semiconductor manufacturing company, where he worked from September 1992 to June 1994. Prior to joining National Semiconductor, Mr. Hart was a private consultant from February 1986 to September 1992 with Hart Weston International, a technology-based management consulting firm. Mr. Hart holds a B.S.E.E. from the University of Washington.

        Hua-Thye Chua, a co-founder of QuickLogic, has served as a member of our board of directors since QuickLogic's inception in April 1988. Since December 1996, Mr. Chua has served as our Vice President, Process Technology. He served as our Vice President of Technology Development from April 1989 to December 1996. During the prior 25 years, Mr. Chua worked at several semiconductor manufacturing companies, including Fairchild Semiconductor, Intel and Monolithic Memories. Mr. Chua holds a B.S.E.E. from Ohio University and an M.S.E.E. from the University of California, Berkeley.

        Carl M. Mills joined QuickLogic in August 2002 as our Vice President, Finance and Chief Financial Officer. From November 2000 to July 2002, Mr. Mills was Vice President of Finance and Chief Financial Officer of AltoWeb, a software company. From November 1987 to September 2000, Mr. Mills held several positions, most recently Vice President of Finance and Chief Financial Officer, at WaferScale Integration, a producer of peripheral integrated circuits. Mr. Mills holds a B.S. degree and an M.B.A. degree from Santa Clara University.

        Timothy Saxe has served as our Vice President, Engineering since November 2001, and as our Vice President, Software Engineering from May 2001 to November 2001. From November 2000 to February 2001, Mr. Saxe was Vice President of FLASH Engineering at Actel, a semiconductor manufacturing company. Mr. Saxe joined Zycad, a design verification tools and services company, in June 1983 and was a founder of Zycad's GateField division, a semiconductor manufacturing division, in 1993. Zycad was renamed GateField in October 1997. Mr. Saxe became GateField's Chief Executive Officer in February 1999 and served in that capacity until GateField was acquired by Actel in

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November 2000. Mr. Saxe holds a B.S.E.E. degree from North Carolina State University, and an M.S.E.E. and a Ph.D. in electrical engineering from Stanford University.

        Jeffrey D. Sexton joined QuickLogic in August 2001. Between January 1995 and August 2001, he held several positions at National Semiconductor including Director of Distribution, Regional Sales Manager, Cisco Systems Global Account Manager and OEM Sales Engineer. Mr. Sexton holds a B.S.E.E. degree from Wright State University in Dayton, OH.

        Reynold W. Simpson has served as our Senior Vice President and Chief Operating Officer since October 2000, and as our Vice President of Operations from August 1997 to October 2000. From February 1996 to July 1997, Mr. Simpson was Vice President of Manufacturing at GateField, a semiconductor manufacturing company. Prior to joining GateField, Mr. Simpson was Operations Manager at LSI Logic, a semiconductor manufacturing company, from March 1990 to February 1996 and Quality Director from February 1989 to March 1990. Mr. Simpson holds a Mechanical Engineering Certificate from the Coatbridge Polytechnic Institute in Scotland, a degree in Technical Horology (mechanical engineering) from the Barmulloch Polytechnic Institute in Scotland and studied for a degree in electronic engineering at the Kingsway Polytechnic Institute in Scotland.

        Arthur O. Whipple has served as our Vice President and General Manager, Logic Products since September 2002, and as our Vice President and General Manager, WebESP from August 2002 to September 2002. Mr. Whipple was our Vice President, Finance and Chief Financial Officer from April 1998 to August 2002. From April 1994 to April 1998, Mr. Whipple was employed by ILC Technology, a manufacturer of high performance lighting products, as its Vice President of Engineering and by its subsidiary, Precision Lamp, a manufacturer of high-performance lighting products, as its Vice President of Finance and Operations. From February 1990 to April 1994, Mr. Whipple served as the President of Aqua Design, a privately-held provider of water treatment services and equipment. Mr. Whipple holds a B.S.E.E. from the University of Washington and an M.B.A. from Santa Clara University.

        Ronald D. Zimmerman has served as our Vice President, Administration since October 1996. From August 1988 to October 1996, Mr. Zimmerman was Human Resources Director of the Analog Products Group at National Semiconductor, as well as group human resources director of the corporate technology and quality/reliability organizations and the human resources director of corporate administration. Mr. Zimmerman holds a B.A. in Sociology and Psychology and an M.A. in Psychology from San Jose State University.

        Donald P. Beadle has served as a member of our board of directors since July 1997. Since June 1994, Mr. Beadle has been President of Beadle Associates, a consulting firm. From October 1994 to December 1996, Mr. Beadle was a consultant for Asian business development at National Semiconductor. At National Semiconductor, he was Managing Director, Southeast Asia from 1993 until June 1994, Vice President of Worldwide Marketing and Sales, International Business Group from 1987 until 1993, and Managing Director, Europe from 1982 to 1986. Mr. Beadle was employed by National Semiconductor in executive sales and marketing positions for 34 years until June 1994, at which time he was Executive Vice President, Worldwide Sales and Marketing. Mr. Beadle received his technical education at the University of Connecticut and the Bridgeport Institute of Engineering.

        Michael J. Callahan has served as a member of our board of directors since July 1997. From March 1990 through his retirement in September 2000, Mr. Callahan served as Chairman of the Board, President and Chief Executive Officer of WaferScale Integration, a producer of peripheral integrated circuits. From 1987 to March 1990, Mr. Callahan was President of Monolithic Memories, now a subsidiary of Advanced Micro Devices, a semiconductor manufacturing company. He was Senior Vice President of Programmable Products at Advanced Micro Devices. From 1978 to 1987, Mr. Callahan held a number of positions at Monolithic Memories including Vice President of Operations and Chief Operating Officer. Prior to joining Monolithic Memories, he worked at Motorola Semiconductor, a

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semiconductor manufacturing company, for 16 years where he was Director of Research and Development as well as Director of Linear Operations. Mr. Callahan serves on the board of Integrated Telecom Express, which provides asymmetric digital subscriber line chipsets, network protocol software, and development tools. Mr. Callahan holds a B.S.E.E. from the Massachusetts Institute of Technology.

        Alan B. Lefkof has served as a member of our board of directors since July 2002. Mr. Lefkof has been the Chief Executive Officer of Netopia, a broadband equipment, software and service provider, since 1994, and has been President and a director of Netopia since 1991. Prior to joining Netopia, Mr. Lefkof served as President of GRiD Systems, a laptop computer manufacturer, and as a Management Consultant at McKinsey & Company. Mr. Lefkof received a B.S. in computer science from the Massachusetts Institute of Technology and an M.B.A. from Harvard Business School.

        Gary H. Tauss has served as a member of our board of directors since June 2002. Since September 2002, Mr. Tauss has been President, Chief Executive Officer and a director of LongBoard, a provider of voice-over-IP infrastructure software solutions. From August 1998 until June 2002, Mr. Tauss was President, Chief Executive Officer and a director of TollBridge Technologies, a provider of voice-over-IP solutions. Prior to co-founding TollBridge, Mr. Tauss was Vice President and General Manager of Ramp Networks, a leading small-office router manufacturer, with responsibility for engineering, customer support and marketing. Mr. Tauss earned both a B.S. and an M.B.A. at the University of Illinois.

Executive Officers

        Our executive officers are elected by, and serve at the discretion of, our board of directors. There are no family relationships among our directors and officers.

ITEM 2. PROPERTIES

        Our principal administrative, sales, marketing, research and development and final testing facility is located in a building of approximately 42,000 square feet in Sunnyvale, California. This facility is leased through 2009 with an option to renew. The acquisition of V3 during 2001 added approximately 11,000 square feet of engineering and development space in Toronto, Canada. The Toronto facility is leased through January 31, 2005. In addition, during 2001 and 2002 we leased approximately 4,000 square feet of engineering development space in La Palma, California near Los Angeles. In December 2001 QuickLogic leased a 4,500 square foot engineering facility in Bangalore, India for the purpose of software development. The Bangalore facility is leased through November 2004. We believe that our existing facilities are adequate for our current needs. In 2002, we closed our offices in La Palma, California and Richardson, Texas.

ITEM 3. LEGAL PROCEEDINGS

        On October 26, 2001, a putative securities class action was filed in the U.S. District Court for the Southern District of New York against some investment banks that underwrote our initial public offering, QuickLogic and some of our officers and directors. This lawsuit is now captioned In re QuickLogic Corp. Initial Public Offering Sec. Litig., Case No. 01-CV-9503. The complaint alleges excessive and undisclosed commissions in connection with the allocation of shares of common stock in our initial public offering and artificially high prices through "tie-in" arrangements which required the underwriters' customers to buy shares in the aftermarket at pre-determined prices in violation of the federal securities laws. Plaintiffs seek an unspecified amount of damages on behalf of persons who purchased our stock pursuant to the registration statements between October 14, 1999 and December 6, 2000. The court has appointed a lead plaintiff in this litigation. On April 19, 2002, plaintiffs filed an amended complaint. Various plaintiffs have filed similar actions asserting virtually identical allegations against over 300 other public companies, their underwriters, and their officers and

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directors arising out of each company's public offering. These actions, including the action against us, have been coordinated for pretrial purposes and captioned In re Initial Public Offering Securities Litigation, 21 MC 92. Defendants in these cases have filed omnibus motions to dismiss on common pleading issues. In October 2002, our officers and directors were voluntarily dismissed without prejudice. Oral argument on the omnibus motion to dismiss was held on November 1, 2002. On February 19, 2003, the court denied in part and granted in part the motion to dismiss filed on behalf of defendants, including us. The court's order did not dismiss any claims against us. As a result, discovery may now proceed. We believe that the allegations against us are without merit and intend to defend the case vigorously.

ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS

        No matters were submitted to a vote of security holders during the fourth quarter of the fiscal year covered by this report.

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PART II

ITEM 5.  MARKET FOR THE REGISTRANT'S COMMON EQUITY AND RELATED STOCKHOLDER MATTERS

        Our common stock has been traded on The Nasdaq Stock Market's National Market under the symbol "QUIK" since October 15, 1999, the date of our initial public offering. The following table sets forth for the periods indicated the high and low closing sales prices for our common stock, as reported on The Nasdaq Stock Market's National Market:

        The last reported sale price of our common stock on The Nasdaq Stock Market's National Market was $0.98 per share on March 7, 2003. As of March 7, 2003, there were 23,758,578 shares of common stock outstanding that were held of record by approximately 270 stockholders.

Dividend Policy

        We have never declared or paid any dividends on our capital stock. We currently expect to retain future earnings, if any, for use in the operation and expansion of our business and do not anticipate paying any cash dividends in the foreseeable future.

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ITEM 6. SELECTED FINANCIAL DATA

(1)

Write-down of marketable securities consists of a charge of $6.8 million and $3.8 million in the years ended December 31, 2001 and 2002, respectively, for the write-down of our equity investment in Tower.

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ITEM 7.  MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS

EXPLANATORY NOTE

        The following Management's Discussion and Analysis of Financial Condition and Results of Operations, as well as information contained in "Risk Factors" below and elsewhere in this Annual Report on Form 10-K, contains "forward-looking statements" within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934. Forward-looking statements are generally written in the future tense and/or are preceded by words such as "will," "may," "should," "could," "expect," "suggest," "believe," "anticipate," "intend," "plan," or other similar words. Forward-looking statements include statements regarding (1) our gross profit and factors that affect gross profit, (2) our ability to control and reduce operating expenses, (3) our research and development efforts, (4) our liquidity, (5) our partners and suppliers, and (6) the commercial success of our products.

        The forward-looking statements contained in this Annual Report involve a number of risks and uncertainties, many of which are outside of our control. Factors that could cause actual results to differ materially from projected results include, but are not limited to, risks associated with (1) our relationship with Tower, (2) the liquidity required to support our future capital requirements, and (3) our ability to maintain a listing on The Nasdaq National Market. Although we believe that the assumptions underlying the forward-looking statements contained in this Annual Report are reasonable, any of the assumptions could be inaccurate, and therefore there can be no assurance that such statements included in this Report will be accurate. In light of the significant uncertainties inherent in the forward-looking statements included herein, the inclusion of such information should not be regarded as a representation by us or any other person that the results or conditions described in such statements or our objectives and plans will be achieved.

Overview

        We design and sell field programmable gate arrays, embedded standard products, associated software and programming hardware. From our inception in April 1988 through the third quarter of 1991, we were primarily engaged in product development. In 1991, we introduced our first line of field programmable gate array products, or FPGAs, based upon our ViaLink technology. We currently have four FPGA product families: pASIC 1, introduced in 1991; pASIC 2, introduced in 1996; and pASIC 3, introduced in 1997. We introduced our Eclipse family of FPGAs in 2000. The newer product families generally contain greater logic capacity, but do not necessarily replace sales of older generation products.

        In September 1998, we introduced QuickRAM, our first line of Embedded Standard Products, or ESPs. Our ESPs are based on our FPGA technology. In April 1999, we introduced QuickPCI, our second line of ESPs. During 2000, we introduced the QuickMIPS and other families of ESPs. ESP products accounted for 37% of total revenue in 2002. We also license our QuickWorks and QuickTools design software and sell our programming hardware, which together have typically accounted for less than 2% of total revenue.

        In April 2001, we signed a definitive agreement with V3 to acquire certain assets of V3 in a stock transaction. We also entered into a manufacturing and distribution agreement with V3 pending the sale in order to ensure continued distribution of V3's products to its customers. V3, based in Toronto, Canada, manufactured ASSPs that enhance high-speed data throughput within telecommunications and Internet infrastructure systems. To facilitate the asset sale and the subsequent windup of V3 as a distinct entity, V3 filed for relief under Chapter 11 of the bankruptcy laws in May 2001. In August 2001, we completed the acquisition of certain assets of V3, for approximately 2.5 million shares of our common stock, valued at $13.1 million. The acquisition has accelerated our ESP strategy by strengthening our ability to develop and market system-level products. On June 20, 2002, V3's plan of reorganization was approved by the bankruptcy court. On May 21, 2002, we filed a Registration Statement on Form S-3 to allow V3 to sell shares to satisfy its creditors in cash. On July 17, 2002, the SEC declared the S-3 effective.

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        On December 12, 2000, we entered into a Share Purchase Agreement, Foundry Agreement and other related agreements with Tower. Under the agreements, we agreed to make a $25 million strategic investment in Tower as part of Tower's plan to build a new wafer fabrication facility. The new fabrication facility is expected to produce 200-mm wafers in geometries of 0.18 micron and below, using advanced CMOS technology from Toshiba.

        In fiscal 2001, we made payments of $14.0 million to purchase shares of common stock and wafer credits from Tower under the agreements. In September of 2001, due to an "other than temporary" decline in the value of the stock, we wrote down its holding value by $6.8 million. At December 31, 2001, QuickLogic's balance sheet reflected 951,926 shares in Tower with a carrying value of $5.4 million, and $1.8 million in wafer credits.

        On May 28, 2002, we entered into an amendment to the original Tower Share Purchase Agreement. Under the amended agreement, Tower agreed to issue shares with a value equal to 60% of the amount of the next two milestone payments due under the agreement, and wafer purchase credits equal to 40% of the payments. The wafer purchase credits issued under the amended agreement can be applied toward wafer purchases from Tower, up to 7.5% of the value of these purchases. After July 1, 2005, they can be applied at up to 15% of the value of the wafer purchases. In addition, Tower released us from its lockup on 700,000 of the previously purchased shares, allowing us to sell these shares on the open market.

        Under the amended agreement, QuickLogic made two payments of $3.7 million each on May 31, 2002 and October 1, 2002. In exchange, we received an additional 805,442 shares and $2.9 million in wafer credits. As of December 31, 2002, we have a remaining payment of $3.7 million that will be payable to Tower under the terms of the amended agreements if Tower meets milestones related to the operation of the fabrication facility prior to July 2003. Even if Tower has not met the milestones, we may invest all or a portion of these funds under renegotiated terms. In December of 2002, due to an "other than temporary" decline in the value of the stock, QuickLogic wrote down the holding value by $3.8 million. At December 31, 2002, QuickLogic's balance sheet reflected 1,757,368 shares in Tower with a carrying value of $6.0 million, and $4.7 million in prepaid wafer credits. Of these shares, 700,000 are available for sale, which are marked to market each reporting period. Any temporary change in the value of these shares is recorded as comprehensive income or loss. As of December 31, 2002 there was no comprehensive income or loss associated with these shares.

        We sell our products through two channels. We sell the majority of our products through distributors who have contractual rights to earn a negotiated margin on the sale of our products. We refer to these distributors as point-of-sale distributors. We defer recognition of revenue for sales of unprogrammed products to these point-of-sale distributors until after they have sold these products to systems manufacturers. We recognize revenue on programmed products at the time of shipment. Approximately 71% of our products sold by point-of-sale distributors are programmed by us and are not returnable by these point-of-sale distributors. We also sell our products directly to systems manufacturers and recognize revenue at the time of shipment. The percentage of sales derived through distributors and direct sales in 2000 was 66% and 34% respectively. In 2001 it was 67% and 33%, respectively, and in 2002, 70% and 30%, respectively.

        Five distributors accounted for 20%, 8%, 7%, 6% and 5% of sales, respectively, in 2000 and four distributors accounted for approximately 22%, 10%, 8%, and 6% of sales, respectively, in 2001. Five distributors accounted for 19%, 12%, 9%, 6% and 6% of sales, respectively, in 2002. We expect that a limited number of distributors will continue to account for a significant portion of our total sales. We believe our products are proprietary and sole source, and that the loss of a particular distributor would not result in a short term disruption in sales of our products, since our customers would either buy our products from another distributor or directly from us.

        A large number of systems manufacturers purchase our products through our distributors or from us directly. One of these manufacturers accounted for 6% of revenue in 2000. Otherwise, individual manufacturers do not typically account for 5% or more of our annual revenue. One customer,

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purchasing ESP products through a distributor, accounted for 12% of fourth quarter 2002 revenue, and we expect that this customer will continue to generate significant revenue through the middle of 2003.

        Our international sales were 38%, 47% and 52% of our total sales for 2000, 2001 and 2002, respectively. We expect that revenue derived from sales to international customers will continue to represent a significant and growing portion of our total revenue. All of our sales are denominated in U.S. dollars.

        Average selling prices for our products typically decline rapidly during the first six to twelve months after their introduction, then decline less rapidly as the products mature. We attempt to maintain gross margins even as average selling prices decline through the introduction of new products with higher margins and through manufacturing efficiencies and cost reductions. However, the markets in which we operate are highly competitive, and there can be no assurance that we will be able to successfully maintain gross margins. Any significant decline in our gross margins will materially harm our business.

        We outsource the wafer manufacturing, assembly and test of all of our products. We currently rely upon TSMC, Cypress and Samsung to manufacture our products, and we rely primarily upon Amkor Technology, ChipPAC, Inc. and ASE to assemble, test and program our products. We expect to manufacture products at Tower in 2003. Our wafer suppliers' lead times are often as long as three months and sometimes longer. In addition, under our arrangements with Cypress and Tower, we are obligated to provide forecasts and enter into binding obligations for anticipated wafer purchases. These long manufacturing cycle times are at odds with our customers' desire for short delivery lead times and as a result we typically purchase wafers based on internal forecasts of demand. In the future, to the extent that we inaccurately forecast total demand or the mix of demand, we may have limited our ability to react to fluctuations in demand for our products, which could lead to excesses or shortages of wafers for a particular product.

Results of Operations

        The following table sets forth the percentage of revenue for certain items in our statements of operations for the periods indicated: