VERISITY LTD - 10-K Annual Report

Israel		Not Applicable
(State or other Jurisdiction of		(I.R.S. Employer
Incorporation or Organization)		Identification No.)

2041 Landings Drive, Mountain View, California		94043
(Address of principal US executive offices)		(Zip Code)

Indicate by check mark whether the registrant: (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. ¨

The aggregate market value of the voting shares held by non-affiliates of the registrant, based upon the closing sale price of the ordinary shares on February 28, 2002, as reported on the Nasdaq National Market, was approximately $130,219,184. Ordinary shares held by each executive officer and director and by each person who owns 5% or more of the outstanding ordinary shares have been excluded in that such persons may be deemed to be affiliates. This determination of affiliates status is not necessarily a conclusive determination for other purposes.

We provide proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to virtually every high growth segment of the electronics industry. Our functional verification products automate critical steps in the process of determining whether systems and integrated circuits, or ICs, conform to their design specifications. By facilitating the identification of design flaws, we enable our customers to deliver higher quality products to market in less time, while helping them to reduce product development costs.

The communications and other segments of the global electronics industry continue to expand rapidly. Within these segments, devices such as high speed network routers, mobile telephones, personal digital assistants and Internet appliances are revolutionizing the way businesses and consumers interact and exchange information. These devices are all examples of complex electronic systems that are comprised of ICs, which implement their key functions. Over the past decade, rapidly growing demand for smaller, faster, more power efficient and increasingly reliable communications and computing devices has created a significant market opportunity for companies to develop more complex systems and ICs that integrate a greater number of highly sophisticated functions.

During the past two decades, systems and the ICs used within them have become increasingly complex in response to business and consumer demand. In 1980, the most complex ICs contained tens of thousands of transistors, which are the basic building blocks of ICs. Today’s most complex ICs contain tens of millions of transistors and are designed to perform a growing number of sophisticated functions. Some of these complex ICs, known as systems-on-chips, or SoCs, integrate a microprocessor, which controls the logic functions of the device, with other functional modules such as memory and digital signal processors onto a single chip. Only a few years ago each of these functions required a separate IC or even an entire circuit board. For instance, today’s most advanced mobile telephones contain a single SoC that performs all the traditional telephone functions and integrates advanced functions such as address books, organizers and web browsers. Consequently, these phones are smaller, more reliable and have longer battery lives than earlier product generations. Dataquest estimates that the worldwide market for SoCs will grow from $20.0 billion in 2000 to $60.0 billion in 2004, which represents a compounded annual growth rate of approximately 32%.

Companies that design and sell ICs often use one or more off-the-shelf design modules to reduce costs and improve time-to-market of their SoC products. These reusable designs, known as intellectual property modules, or IP cores, can include microprocessors, communication cores and other functional modules and are often licensed from independent third parties, known as IP providers. The growth in demand for complex ICs, particularly SoCs, has created an increased need for IC designers to quickly and accurately integrate IP cores onto a single chip. Dataquest estimates that the third party market for IP cores grew from $492.4 million in 1999 to approximately $689.9 million in 2000, which represents an annual growth of 40%.

Every new system, IC and IP core design must be verified to detect and eliminate discrepancies, known as design flaws, between the specifications and the implementation of its design to ensure that the manufactured device functions properly. Functional verification is the engineering process of determining whether a system, IC or IP core design behaves as described in its specifications. As new generations of systems and ICs expand in complexity, their designs pose far greater challenges to functional verification due to greater numbers of

transistors, the integration of reusable IP cores and more elaborate SoC designs. These sources of additional complexity place a greater burden on the tools and resources that engineers typically employ in the functional verification of each new system and IC design.

For most of the past decade, the functional verification process has generally relied upon software simulators to mimic the behavior of the design. To identify design flaws, engineers use these simulators to run a large number of different test scenarios against descriptions of the design that are typically written in special-purpose software languages. Engineers who use this approach to functional verification create test plans that attempt to both identify the most important areas of the design for testing and describe numerous real world scenarios that the design must be capable of addressing.

As designs have become increasingly more complex, creating the number and types of test scenarios sufficient to identify all potential design flaws has become far more challenging. As a result, system and IC designers have deployed more engineering and computing resources to address functional verification. Today, functional verification typically accounts for between 50% and 70% of the total development resources devoted to electronic systems and complex ICs. In many cases, the design verification team is now larger than the team of engineers that creates the design for the system or IC. This has created a shortage of trained verification engineers, resulting in a significant bottleneck in the overall time-to-market for many new products. Dataquest identifies ESL (Electronic System Level) solutions as a “must-have weapon” in verification. They report that the ESL Test and Verification market (in which we sell our products) continues to grow and is expected to expand at a compounded annual growth rate of over 27% from 2001 through 2005.

Traditionally, companies that design and sell systems and ICs, known as systems and IC companies, developed many of their own functional verification tools. In-house tools are generally not sophisticated enough to handle today’s complex system and IC designs. Functional verification using these tools tends to be manual and time consuming and often fails to find many elusive design flaws, such as ambiguous specifications and unforeseen usage scenarios. Without automated tools and an effective functional verification methodology, engineers often have great difficulty detecting many design flaws in systems and ICs before they are manufactured.

Design flaws that are discovered in the manufactured device can be costly, requiring the redesign and remanufacture of the IC, a process commonly referred to as a re-spin. Multiple re-spins are common before the first commercial shipment. In November 1999, Dataquest estimated that the cost for each re-spin of a typical 0.18 micron application-specific IC is $500,000. Re-spins also disrupt production planning and consume valuable engineering resources.

We provide proprietary technologies and software products that address the growing need for improved functional verification of the system and IC designs essential to the communications and other high growth segments of the electronics industry. Our functional verification products, led by our top selling Specman Elite product, automate and enhance the process of detecting design flaws in systems and ICs before they are manufactured and enable our customers to deliver more reliable products with reduced time-to-market and product development costs.

Our business objective is to establish our proprietary technologies and software products as the industry standard for the functional verification of system, IC and IP core designs required by the communications and other high growth segments of the electronics industry. To achieve this objective, we intend to pursue the following key business strategies:

In order to proliferate our products, we are leveraging marketing and sales channels outside of our organization that we believe will enable us to accelerate our sales growth. To carry out our strategy, we have created and implemented the following programs and alliances:

Specman Elite utilizes e, a specialized functional verification software language that we have developed. We are promoting the use of e as the industry standard verification language with a goal of ensuring the interoperability of our products with emerging technologies and building greater barriers to competition. The elements of this strategy include:

We believe that we are a technology leader in the functional verification market segment and that we have one of the largest and most experienced engineering teams focused solely on this segment. We intend to maintain this position by enhancing our understanding of the challenges facing verification engineers within our customer base and by responding with product innovations based on leading-edge research and development. We believe that by continuing to work closely with our systems and IC customers, we will be able to develop product innovations specific to their particular requirements. We will continue to invest in research and development and customer-focused innovations to extend the capabilities of our products, and introduce new ones, while expanding interoperability with complementary third-party products.

We will continue to focus our research and development efforts on product innovations targeting high growth market segments such as communications, consumer electronics and computers. Within these market segments, we will continue to focus our sales and marketing efforts on industry leaders. We also plan to maximize the proliferation of our products and encourage their widespread adoption within key targeted customers. In addition, we will continue to enhance existing products and develop new ones that are particularly focused on the functional verification needs of our targeted customer base.

Our top selling Specman Elite software product automates the overall process of functional verification at all levels of design: system, IC and module. Specman Elite improves the overall quality of a design by detecting many subtle design flaws through its ability to rapidly generate real world test scenarios for the design being verified. It also increases engineering productivity by automating manual processes such as developing verification environments, generating tests, checking results and analyzing coverage.

Our e language is the platform for powerful, reusable verification environments that allows Specman Elite to automate functional verification. e enables engineers to efficiently extract and describe the rules from a design project’s specifications, such as restrictions on inputs, protocols and test scenarios. With this input, Specman Elite automates the functional verification of a design. e provides a more intuitive approach that enables engineers to develop their verification environments with significantly fewer lines of software code.

In addition, Specman Elite enables engineers to reuse portions of a verification environment for multiple design projects, as well as for various phases of a single project. These phases may include verifying the design of IP cores and other modules, integrating modules into complex ICs and integrating multiple ICs into a complex system.

Our Verification Advisor product provides our customers with an extensive collection of verification methodologies designed to accelerate the use of our Specman Elite product. These methodologies and example templates written in e reflect our recommended “best practices” to address real world functional verification problems. These are organized in an easy-to-use database accessible via any standard web browser. For example, an engineer who needs to verify the integration of an Ethernet interface could access Verification Advisor to quickly find a customizable verification environment template for that purpose. In many cases, Verification Advisor reduces the amount of time needed to create verification environments. Furthermore, because Verification Advisor accelerates the learning process of engineers, it decreases our cost of customer support.

e verification components, or eVCs, are pre-verified, reusable pieces of verification code written in e. Verification engineers use eVCs with Specman Elite to significantly shorten the time it takes to create many verification environments. eVCs are used primarily within the communications and other high growth segments of the electronics industry that are dependent on standard interfaces such as PCI, Ethernet, USB and ARM AMBA.

eCelerator is our testbench acceleration tool that gives customers access to the automated verification capabilities of Specman Elite in combination with the high performance of hardware-assisted verification. The testbench acceleration enabled by eCelerator allows verification engineers to run portions of test scenarios written in the e verification language on standard hardware verification platforms, known as emulators or accelerators. The ability to accelerate the simulation of testbenches is particularly critical when verifying the designs of very large or complex systems and SoCs.

Our Invisible Specman product is a special purpose version of Specman Elite that verifies IP core integration within SoC designs. Invisible Specman simplifies the effort required to integrate IP cores by operating as a seamless and invisible portion of the verification environment during simulation, with minimal user interaction other than alerting the user whenever it discovers an integration flaw in the design. As part of our Pure IP program, we license Invisible Specman to IP providers, which bundle the software with their IP cores as

Our SureLint functional verification software product enables engineers to detect certain classes of design flaws prior to simulation. SureLint helps the user identify the cause and suggests possible solutions to these design flaws. By detecting these design flaws even prior to simulation, it is easier to debug system and IC designs, improving the overall efficiency of the verification process.

Our SureCov software product is fully automated and enables engineers to determine the extent to which their design code has been simulated. SureCov allows engineers to distinguish which portions of the design code have been sufficiently exercised and which require further effort. In addition, SureCov provides engineers with the ability to determine if any tests are redundant, and to define an optimal sequence of tests, in order to save valuable simulation time.

Our functional verification products are designed to enable ease of use, to increase the productivity of our customers’ engineers and to comply with industry standards. Our customers use our products to verify the designs of systems, ICs and IP cores developed by their engineers. We recognize that each of our customers has specific requirements and issues that need to be addressed during both the initial implementation of our functional verification technology and the ongoing use of it. We believe that a high level of customer service and support is critical to our continued success. As a result, we have developed and continue to enhance our customer service and support programs to address our customers’ needs. Our highly trained field consulting engineers perform pre-sales and post-sales application support from a number of geographic locations.

We also support customers who license our products through paid maintenance and support services, which include periodic product updates, if and when available and remote technical support through electronic mail and telephone hotlines from our Mountain View, California and Rosh Ha’ain, Israel locations. These support services are generally sold when one of our customers purchases either a time-based license or a perpetual license to use our products. Each year, we have released one or more new updates to our products. Our customers with perpetual licenses or time-based licenses with terms greater than one year may elect to renew maintenance on an annual basis.

We license our functional verification products to the designers of systems, ICs and IP cores, for use in products specifically developed for the communications, computers, business automation and consumer electronics markets. Within these market segments, our customers can use our products to verify designs in the following applications:

Through our Pure IP program, we build alliances with Specman Elite customers that are either influential independent IP providers or semiconductor companies that also provide IP cores. These companies, which include ARM, LSI Logic, MIPS Technologies and Rambus, can deliver our Invisible Specman product as part of the verification toolkits they deliver to their IP customers. They benefit from participating in our program by reducing the cost of supporting their IP customers through the difficult task of verifying the integration of the provider’s IP cores into their customers’ designs. We benefit from our Pure IP program by obtaining significant industry endorsements from these influential leaders in the semiconductor and independent IP provider industries. This usage and endorsement generates greater market demand for Specman Elite.

Our LicenseE program enables tool vendors to license our e language for use as an interface to their products. These vendors benefit by leveraging our existing customer base familiar with e in an effort to proliferate their products more rapidly. We benefit by further proliferating e as an industry standard, and by improving the interoperability of our products with those of other vendors. Among the several companies that have participated in this program, include: @HDL, Axis Systems, Mentor Graphics, Novas Software, SynaptiCAD, Synopsys, Theras Systems and Veritools.

To improve time-to-market and to supplement their internal engineering resources, a growing number of companies that design systems and ICs utilize outside consultants for assistance with their functional verification efforts. Through our Verification Alliance program, we enroll many consulting organizations that perform contract verification work. The consultants benefit from the program by obtaining access to our suite of advanced verification products and our existing customer base. The program helps us proliferate our functional verification tools and underlying methodologies, including the e verification language. We currently have over 65 consulting organizations and consultants enrolled in the program, located in the United States, Europe, Israel and Japan. In addition, several of these companies are now developing commercial eVCs as part of their business model.

Our University Program was developed to support educational institutions in their verification-related education and research. The program unites us with universities all over the world in providing engineers with open access to our tools and the e verification language. Initial members in the program include: Chemnitz University of Technology, Ecole Polytechnique de Montreal, India Institute of Technology Bombay, Institute of Microelectronic Circuits and Systems (IMS), Institute for System Level Integration, McGill University, Technion-Israel Institute of Technology, University of Michigan and University of Tübingen.

Today’s functional verification methods integrate several technologies and products from multiple vendors to form a single solution. Because our products are designed to automate the process of functional verification, they must interoperate with all common verification tools. In this respect, we have developed many interfaces, and are members of the key industry interoperability programs, including the Cadence Connections Program with Cadence Design Systems, the in-Sync Program from Synopsys and the OpenDoor Program from Mentor Graphics. In addition, we have an interoperability program for companies in the Electronic Design Automation industry called VIP (Verisity Interoperability Partners) to enable other companies in that industry to develop and test integrations to our products. Current members in the VIP program include: 0-in, @HDL, Aldec, American Arium, Axis Systems, Cadence Design Systems, Co-Design Automation, CoWare, Denali Software, Fintronic, Ikos Systems, Mentor Graphics, Novas Software, SynaptiCAD, Synopsys, Tharas Systems and Veritools. We have also formed deeper alliances with several companies that provide for the joint development and marketing of solutions and often extend into channel cooperation and training. These alliances help us supplement our

We focus our marketing efforts on creating and increasing market awareness of our products and generating leads for our sales organization. Our marketing strategy is designed to proliferate market acceptance for our functional verification solutions by creating programs such as Pure IP, Verification Alliance, University Program, VIP and LicenseE program.

We employ a wide variety of marketing communications channels to inform existing customers and potential new customers about our products. These channels include trade shows, print and web advertising, our website, public relations, hosting user conferences and publication of our quarterly newsletter.

We license our software products to customers primarily through our direct sales organization. As of December 31, 2001, our direct sales staff totaled 65 employees located in 17 sales offices. Our sales staff includes both sales personnel and consulting engineers, who are our field engineers. We also rely on an outside telesales operation to help generate evaluations of our SureCov and SureLint products that are licensed to customers.

Our sales personnel and consulting engineers operate out of our sales and customer support offices in the following North American locations: Austin, Texas; Chicago, Illinois; Dallas, Texas; Denver, Colorado; Mountain View, California; Ottawa, Canada; Phoenix, Arizona; Portland, Oregon; Research Triangle Park, North Carolina; San Diego, California; Morristown, New Jersey and Westborough, Massachusetts. In Europe, we have sales and customer support centers in London, England; Munich, Germany and Paris and Grenoble, France. We also have a regional sales and support office in Rosh Ha’ain, Israel.

We also sell our products through independent sales representatives and distributors. We have a sales representative that covers Japan on an exclusive basis with respect to Specman Elite and on a non-exclusive basis with respect to our SureCov and SureLint products. This representative also has an office in San Jose, California to maintain a sales and customer support relationship with predominantly Japanese systems and semiconductor companies that do business in the San Jose metropolitan area. We also have a non-exclusive representative in Scandinavia, India and Taiwan. We distribute our products through an exclusive distributor located in Korea. These outside sales representative and distributor organizations also have technical support resources. Our revenue through these indirect channels accounted for 16.6% of our total revenue in 1999, 17.0% of our total revenue in 2000 and 11.8% of our total revenue in 2001.

The functional verification market is highly competitive and is characterized by rapid technological innovation and frequently emerging new suppliers. We directly compete with large vendors of design and verification tools such as Synopsys and Cadence Design Systems. We also compete with a number of smaller verification tool vendors. In addition, we face competition from within our potential new customers, in the form of the in-house verification engineering teams of major systems and IC companies that use and promote their own internally-developed functional verification tools. One of our largest competitive challenges is to convince these engineering teams that our products are superior to their internal verification tools.

reputation within the installed customer base, customer service and support, access to customers, expertise, regional sales and technical support and price. We believe that we compete favorably with respect to these factors. However, we believe that we will continue to experience increased competition from both existing and potential new entrants into the functional verification market, some of which may have longer operating histories, greater overall brand recognition and significantly greater financial and marketing resources.

Our Specman Elite software product is the first commercial solution that combines the key technologies needed to automate functional verification. These innovative technologies include constraint-driven test generation, data and temporal checking and functional coverage analysis. The test generator can create test data according to a series of constraints that allow for a relatively concise description of valid or even invalid input states. It will work within these constraints to automatically generate any number of test values. A relatively simple modification of selected constraints directs the generated values to focus on selected functions of the design being tested. Temporal checking allows an engineer to monitor certain events within a stated time period. The functional coverage analysis shows an engineer what functionality has or has not been exercised during simulations. The engineer can modify the test constraints to direct testing at any desired function or portion of a device being tested, and the functional coverage analysis can highlight additional areas the engineer should consider.

Another important technology innovation within Specman Elite is the e language. This software language, which directs the Specman Elite functions, is particularly well suited for the description of hardware behavior, including time-related and hardware function elements, as well as specific features for verification.

Our eCelerator software product is the first commercially available testbench synthesis tool. This product allows verification engineers to partition, synthesize and run portions of an e testbench, which is the input to Specman Elite, on verification hardware known as accelerators and emulators. Hardware accelerators and emulators significantly improve the speed of testbench simulation and thereby reduce the engineering time needed for design simulation and verification. This gives customers access to the automated verification features of Specman Elite at significantly higher levels of performance.

Our SureLint software product detects a variety of design flaws prior to simulation. SureLint provides the ability to choose which rules should be applied to different portions of the design. One of SureLint’s key technologies enables the detection and diagnosis of unstable conditions within a design. This is a valuable feature to a design engineer because it highlights situations in which the state of an internal point in a design might change depending on how fast each of several paths within the design operates, which would indicate a design flaw in the final product.

Our SureCov software product automatically measures the completeness of functional verification according to nine separate metrics, including code coverage and finite state machine analysis. Code coverage indicates the lines of code actually executed during simulation. Finite state machines are key components of the design that indicate its internal control flow. SureCov indicates the coverage of design states and the transition between those states.

Our research and development expenses were $4.9 million in 1999, $7.3 million in 2000 and $8.9 million in 2001. We expect that these costs will increase in the future as we attempt to maintain a leading technology position in the functional verification market. As of December 31, 2001, we had more than 60 employees engaged in research and development activities.

We rely primarily on a combination of nondisclosure agreements and other contractual provisions, as well as patent, trademark, trade secret and copyright law to protect our proprietary rights. Our general policy has been to seek patent protection for those inventions and improvements likely to be incorporated in our technologies or otherwise expected to be of value. We have an active program to protect our proprietary technology through the filing of patents.

As of February 28, 2002, we have four patents issued in the United States and 14 patent applications on file with the USPTO. Once granted, the duration of each patent will be up to 20 years from the effective date of filing of the applications. Our earliest two issued patents can remain effective until August 7, 2017 and until February 6, 2018. Although we have no patents issued in any other jurisdiction, we have two patent applications on file with the European Patent Office, four patent applications on file under the Patent Cooperation Treaty process, one Israeli patent application and one Japanese patent application. These patents, if granted, will allow us to take legal action against others who may infringe on our core technologies covered by the patent claims. We intend to continue to file patent applications as appropriate in the future. We cannot be sure, however, that any of our pending patent applications will be allowed other than the four that have already been allowed by the USPTO, that any issued patents will protect our intellectual property or will not be challenged by third-parties, or that the patents of others will not seriously harm our ability to do business. In addition, others may independently develop similar or competing technologies or design around any of our patents.

In addition, as of February 28, 2002, we had five United States trademark registrations with respect to our Verisity and Sure branded products, and we had one pending United States trademark applications on file with the USPTO. In addition, we had approximately 18 additional applications pending or registrations granted in various countries where we focus our sales efforts, specifically for Verisity, Specman, Specman Elite, Invisible Specman, and other important corporate names. These existing registrations, and those that may be granted in the future, will improve our ability to take legal action against others who may use these or similar marks on similar goods and services in the respective countries. However, unlike patents, in the United States and in some foreign countries we may have certain rights with respect to our trademarks even though they are not registered with the respective national trademark offices. We cannot be sure that the USPTO or other national trademark offices will issue registrations for any of our pending trademark applications. Further, any trademark rights we hold or may hold in the future may be challenged or may not be of sufficient scope to provide meaningful protection.

We protect the source code of our software products as both trade secrets and unpublished copyrighted works. We license the object code to our customers for limited uses and maintain contractual controls over the use of our software. Wide dissemination of our software may make protection of our proprietary rights difficult, particularly in jurisdictions outside the United States that may be less likely to enforce copyrights owned by foreign parties against local infringers. Although most of our customers have signed license agreements which may further protect our copyrights and trade secrets beyond the protections afforded by applicable law, not all of our customers have signed such agreements.

Others may still gain access to our trade secrets or discover them independently. Should any of our customers that have not signed a license agreement or nondisclosure agreement disclose to third-parties any of our information that we regard as trade secrets, we may be unable to enforce our trade secret rights with respect to such information.

Although we believe that our technologies do not infringe on any copyrights or other proprietary rights of third-parties, we cannot be certain that we will not infringe upon the intellectual property rights of third parties, including our competitors, who may assert patent, copyright and other intellectual property rights to technologies, code, features or other product elements that are important to us. The costs of defending our

proprietary rights or claims that we infringe third-party proprietary rights may be high. Also, if we are unsuccessful in defending against third-party infringement claims, we could be legally prevented from continuing to license our software products to the extent they contain technologies, code, features or other elements that are determined by the courts to infringe the proprietary rights of such third parties.

As of December 31, 2001, we employed 182 people, of whom 109 worked in North America, 58 worked in our Israeli facilities and 15 worked in Europe. Of the North American employees, 62 were in sales and marketing, including 26 consulting engineers, 19 were in research and development, 13 were in general and administration and 15 were in technical customer support. Our employees in Israel worked primarily in research and development. Our employees in Europe worked primarily in sales and customer support. Our employees are not represented by a collective bargaining agent, except as may be required by government legislation or regulation. We consider our relations with our employees to be good, and we will continue to strive to provide a positive working environment for our employees.

Name	Age	Position
Moshe Gavrielov	47	Chief Executive Officer and Director
Yoav Hollander	48	Chief Technical Officer and Director
Charles Alvarez	52	Vice President of Finance and Administration, Chief Financial Officer and Secretary
Ziv Binyamini	41	Vice President of Research and Development
Francine Ferguson	37	Vice President of Worldwide Marketing
Lawrence Lapides	41	Vice President of Sales
Michael McNamara	40	Senior Vice President of Technology and Director
Pierre Lamond(1)	71	Director
Zohar Zisapel(1)(2)	53	Director
Tali Aben(1)(2) (3)	38	Director
Amos Wilnai(2)(3)	62	Director

Moshe Gavrielov has served as our Chief Executive Officer and Director since March 1998. From November 1988 to March 1998, Mr. Gavrielov worked at LSI Logic Corporation where he held several executive management positions, including Executive Vice President of Products, Senior Vice President of International Markets, Senior Vice President and General Manager of LSI Logic Europe and General Manager of the ASIC division. Mr. Gavrielov holds a Bachelor of Science degree in Electrical Engineering and a Masters of Science degree in Computer Science from the Technion Israel Institute of Technology (IIT) in Haifa, Israel.

Yoav Hollander is our co-founder and has served as our Chief Technical Officer and Director since our inception in September 1995. From 1990 to our inception, Mr. Hollander was a consultant for various semiconductor companies including National Semiconductor Corporation and Digital Equipment Corporation. Mr. Hollander worked on the development of the verification environment employed by the Israeli design center of Digital Equipment Corporation for pre- and post-silicon testing of their designs. Mr. Hollander holds a Bachelor of Science degree in Computer Science from Ben Gurion University in Be’er Sheva, Israel.

Charles Alvarez has served as our Vice President of Finance and Administration and Chief Financial Officer since June 1998. From March 1997 to June 1998, Mr. Alvarez served as Vice President of Finance and Administration and Chief Financial Officer at Alliance Semiconductor. From October 1989 to March 1997, Mr. Alvarez served as Senior Director of Finance and Operations for LSI Logic Corporation. Mr. Alvarez holds a Bachelor of Arts degree and a Masters of Arts degree in Business and Economics from San Francisco State University.

Ziv Binyamini has served as our Vice President of Research and Development since October 1998. From November 1997 to October 1998, Mr. Binyamini served as our principal researcher. From July 1997 to November 1997, he was a researcher at Intel Corporation. From July 1994 to July 1997, Mr. Binyamini co-managed the Logic Verification CAD group at Intel Design Technology in Haifa, Israel. Mr. Binyamini holds a Bachelor of Science degree in Computer Science and Mathematics from Bar Ilan University in Ramat Gan, Israel.

Francine Ferguson has served as our Vice President of Worldwide Marketing since January 1999. From May 1997 to January 1999, Ms. Ferguson served as our Director of Product Marketing. From March 1996 to May 1997, Ms. Ferguson was a Product Line Manager and from January 1995 to March 1996, she was Senior Product Marketing Manager at Synopsys, Inc. Ms. Ferguson has spent over 14 years in the design automation industry in the areas of software development and marketing for verification and synthesis products. Ms. Ferguson holds a Bachelor of Science degree in Computer Science from Columbia University, School of Engineering and Applied Science.

Lawrence Lapides has served as our Vice President of Sales since our acquisition of SureFire Verification in November 1999, where he served in the same capacity from July 1998 to November 1999. From May 1991 to June 1998, Mr. Lapides served as Director of North American Sales for Exemplar Logic. Mr. Lapides holds a Bachelor of Arts degree in Physics from the University of California, Berkeley, a Masters of Science degree in Applied and Engineering Physics from Cornell University, and a Masters degree in Business Administration from Clark University.

Michael McNamara has served as our Senior Vice President of Technology and Director since our acquisition of SureFire Verification in November 1999, where he served as President, Chairman of the Board, and co-founder from April 1996 to November 1999. From June 1995 to April 1996, Mr. McNamara served as a Director and a consultant at Verilog Consulting Services, Inc. From April 1994 to May 1995, Mr. McNamara served as Vice President of Engineering at ViewLogic, Inc. Mr. McNamara holds a Bachelor of Science degree and a Masters of Engineering degree in Electrical Engineering from Cornell University.

Pierre Lamond has served as our Director since August 1997. Mr. Lamond has served as a General Partner of Sequoia Capital, a venture capital firm, since 1981. Mr. Lamond serves on the Board of Directors of Vitesse Semiconductor Corp. and Redback Networks, Inc. Mr. Lamond holds a Bachelor of Science degree in Electrical Engineering, a Master of Science degree in Physics from Toulouse University and a Masters of Science degree in Electrical Engineering from Northeastern University.

Zohar Zisapel has served as our Director since August 1997. Mr. Zisapel serves on the Board of Directors of Ceragon Networks, Radvision Ltd., Radware Ltd., Radcom Ltd., RIT Technologies, Ltd. and Silicom Ltd. Mr. Zisapel is a founder and Director of Rad Data Communications and has served as its President and Chairman since 1982. He also served as Chairman of the Israeli Association of Electronics and Software Industries. Mr. Zisapel holds an Masters of Science degree in Electrical Engineering from the Technion Israel Institute of Technology (IIT) in Haifa, Israel and a Masters degree in Business Administration from Tel Aviv University in Tel Aviv, Israel.

Tali Aben has served as our Director since December 1996 and as an external director since March 2001. Ms. Aben has been a General Partner at Gemini Israel Funds, an Israeli venture capital firm, since October 1994. Ms. Aben holds a Bachelor of Science degree in Mathematics and Computer Science and a Masters degree in Business Administration from Tel Aviv University in Tel Aviv, Israel.

Amos Wilnai has served as an external director since March 2001. Mr. Wilnai founded and has served as the Chairman of the Board of Directors of MMC Networks, Inc. since September 1992. From October 1998 to April 1999, Mr. Wilnai served as Acting Chief Executive Officer at MMC Networks. From September 1994 to June 1998, he served as Executive Vice President of Business Development at MMC Networks. From September 1992 to October 1994, he served as President at MMC Networks. Mr. Wilnai also serves as an advisor to the Board of Governors of the Bird Foundation (Israel-US Binational Industrial Research and Development Foundation). Mr. Wilnai holds a Bachelor of Science degree in Electrical Engineering from the Technion Institute of Technology (ITT) in Haifa, Israel and a Masters of Science degree in Electrical Engineering from the Polytechnic Institute in Brooklyn.

All of our operations are conducted in leased office facilities. Our principal executive offices in the U.S. occupy approximately 20,000 square feet and are located in Mountain View, California. These offices house substantially all of our marketing, administration, finance, customer service and support employees and approximately one-fifth of both our sales employees and research and development team. Our lease for the Mountain View facility expires on December 31, 2003.

In addition, we lease two facilities with a total of approximately 12,000 square feet in Rosh Ha’ain, Israel, approximately 10 miles from Tel Aviv. Those facilities house a substantial portion of our research and development employees and a portion of our customer service and support team. One of these leases, for approximately 9,720 square feet of space, expires on February 28, 2003, with options for two consecutive two-year extensions. The second lease, for approximately 2,200 square feet of space, expires on December 15, 2002, with an option for a single two-year extension.

We also occupy an additional 3,200 square feet of office space in Massachusetts where we maintain our East Coast operations under a lease which expires on March 31, 2006 and 3,300 square feet of office in Austin, Texas under a lease agreement which expires on December 31, 2004. In addition, we occupy less than 1,000 square feet of space in each of our small regional sales offices located in Paris and Grenoble, France; London, England; Munich, Germany; Morristown, New Jersey and Austin and Dallas, Texas; each under leases for a term not exceeding one year. We believe that our existing leased office space will provide us with adequate facilities for our anticipated growth through at least 2002.

In April 2001, the underwriters of the initial public offering exercised their over-allotment option to purchase an additional 500,250 ordinary shares at $7.00 per share, the initial public offering price of the ordinary shares. The net proceeds received after deducting underwriting discounts were approximately $3.3 million.

We intend to use the aggregate net proceeds from our initial public offering for general corporate purposes, capital expenditures and potential acquisitions of complementary businesses, products and technologies. Pending these uses, the net proceeds of the offering have been and will continue to be invested in interest bearing, investment grade securities.

Our ordinary shares are listed and traded on the Nasdaq National Market under the symbol “VRST”. The following table sets forth, for the periods indicated, the range of high and low daily closing prices for our ordinary shares as reported by the Nasdaq National Market.

Since our inception, we have not declared or paid any cash dividends on our ordinary shares. We do not anticipate paying any cash dividends on our ordinary shares in the foreseeable future and intend to retain our future earnings, if any, to finance the development of our business. In addition, we are subject to the following restrictions on the declaration and payment of our dividends:

In the event that we elect to declare dividends, we will pay those dividends in United States dollars to our shareholders which are not Israeli residents. Under current Israeli law, any dividends or other distributions paid in respect of our share capital may be freely paid in non-Israeli currencies at the prevailing rate of exchange, provided that Israeli income tax has been withheld or paid from any distributions. As a result, a non-Israeli resident shareholder will be subject to the risk of currency fluctuation between the date a dividend is declared and the date the dividend is paid.

The selected consolidated financial data below should be read in conjunction with “Management’s Discussion and Analysis of Financial Condition and Results of Operations” and our consolidated financial statements and the related notes. The selected consolidated statements of operations data for the years ended December 31, 1999, 2000, and 2001, and the selected consolidated balance sheet data as of December 31, 2000 and 2001, are derived from, and are qualified by reference to, the audited consolidated financial statements included elsewhere in this Form 10-K. The historical financial information for all periods includes the operations of SureFire Verification, Inc., which we acquired on November 30, 1999. The transaction was accounted for using the pooling-of-interests method. The selected consolidated statement of operations data for the years ended December 31, 1997 and 1998, and the selected consolidated balance sheet data as of December 31, 1997, 1998 and 1999, are derived from our audited consolidated financial statements that are not included in this Form 10-K. The historical results presented below are not necessarily indicative of future results. (Although we were founded in September 1995, we had no operations until January 1996.)

	Year Ended December 31,
	1997		1998		1999		2000		2001
	(in thousands, except per share data)
Consolidated Statements of Operations Data :
Revenue	$	4,025	$	7,075	$	11,477	$	21,499	$	38,737
Cost of revenue		1,092		1,853		1,907		2,492		3,432
Gross profit		2,933		5,222		9,570		19,007		35,305
Operating expenses:
Research and development, net		1,794

PART I

Item 1.	Business	3
Item 2.	Properties	15
Item 3.	Legal Proceedings	15
Item 4.	Submission of matters to a vote of security holders	15

PART II

Item 5.	Market for registrant’s ordinary equity and related shareholder matters	16
Item 6.	Selected financial data	17
Item 7.	Management’s Discussion and Analysis of Financial Condition and Results of Operations	19
Item 7A.	Qualitative and Quantitative Disclosures About Market Risk	29
Item 8.	Financial statements and supplementary data	38
Item 9.	Changes in and disagreements with accountants on accounting and financial disclosure	39

PART III

Item 10.	Directors and executive officers of the registrant	40
Item 11.	Executive compensation	40
Item 12.	Security ownership of certain beneficial owners and management	40
Item 13.	Certain relationships and related transactions	40

PART IV

Item 14.	Exhibits, financial statements schedules and reports on Form 8-K
	Financial Statements and report of Ernst & Young LLP, Independent Auditors	41
	Index to Exhibits	41

Signatures		44

Index to consolidated financial statements		F-1

REPORT OF ERNST & YOUNG LLP, INDEPENDENT AUDITORS		F-2

	High		Low
April 1, 2001–June 30, 2001	$	19.610	$	8.438
July 1, 2001–September 30, 2001	$	18.050	$	6.599
October 1, 2001–December 31, 2001	$	19.440	$	7.250