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UNITED STATES SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549
Form 10-K
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ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE
SECURITIES EXCHANGE ACT OF 1934 |
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For the fiscal year ended January 2, 2005 |
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TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE
SECURITIES EXCHANGE ACT OF 1934 |
Commission file number 0-21970
ACTEL CORPORATION
(Exact name of Registrant as specified in its charter)
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California
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77-0097724 |
(State or other jurisdiction of
incorporation or organization) |
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(I.R.S. Employer
Identification No.) |
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2061 Stierlin Court
Mountain View, California
(Address of principal executive offices) |
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94043-4655
(Zip Code) |
(650) 318-4200
(Registrant’s telephone number, including area code)
Securities registered pursuant to Section 12 (b) of
the Act:
None
Securities registered pursuant to Section 12(g) of the
Act:
Common Stock, $.001 par value
Preferred Stock Purchase Rights
(Title of class)
Indicate by check mark whether the Registrant (1) has filed
all reports required to be filed by Section 13 or 15(d) of
the Securities Exchange Act of 1934 during the preceding
12 months (or for such shorter period that the Registrant
was required to file such reports) and (2) has been subject
to such filing requirements for the past
90 days. Yes þ No o
Indicate by check mark if disclosure of delinquent filers
pursuant to Item 405 of Regulation S-K is not
contained herein, and will not be contained, to the best of
Registrant’s knowledge, in definitive proxy or information
statements incorporated by reference in Part III of this
Annual Report on Form 10-K or any amendment to this
Annual Report on
Form 10-K. þ
Indicate by check mark whether the registrant is an accelerated
filer (as defined in Rule 12b-2 of the Exchange
Act). Yes þ No o
The aggregate market value of the voting stock held by
non-affiliates of the Registrant, based upon the closing price
for shares of the Registrant’s Common Stock on
July 5, 2002, as reported by the National Market
System of the National Association of Securities Dealers
Automated Quotation System, was approximately
$371,000,000. In calculating such aggregate market value,
shares of Common Stock owned of record or beneficially by all
officers, directors, and persons known to the Registrant to own
more than five percent of any class of the Registrant’s
voting securities were excluded because such persons may be
deemed to be affiliates. The Registrant disclaims the existence
of control or any admission thereof for any purpose.
Number of shares of Common Stock outstanding as of
March 3, 2005: 25,167,938.
In this Annual Report on Form 10-K, Actel Corporation
and its consolidated subsidiaries are referred to as
“we,” “us,” “our,” or
“Actel.” You should read the information in this
Annual Report with the Risk Factors at the end of Item 1.
Unless otherwise indicated, the information in this Annual
Report is given as of March 3, 2005, and we undertake no
obligation to update any of the information, including
forward-looking statements. All forward-looking statements are
made under the safe harbor provisions of the Private Securities
Litigation Reform Act of 1995. Statements containing words such
as “anticipates,” “believes,”
“estimates,” “expects,” intends,”
“plans,” “seeks,” and variations of such
words and similar expressions are intended to identify the
forward-looking statements. The Risk Factors could cause actual
results to differ materially from those projected in the
forward-looking statements.
TABLE OF CONTENTS
PART I
Overview
We design, develop, and market field programmable gate arrays
(FPGAs) and supporting products and services. FPGAs are used by
manufacturers of automotive, communications, computer, consumer,
industrial, military and aerospace, and other electronic systems
to differentiate their products and get them to market faster.
We are the leading supplier of FPGAs based on Flash and antifuse
technologies, and believe that we are the leading supplier of
high reliability FPGAs. Our strategy is to offer innovative
solutions to markets in which our technologies have a
competitive advantage, including the value-based and
high-reliability FPGA markets. In support of our FPGAs, we offer
intellectual property (IP) products; design and development
software; programming hardware; debugging tool kits and
demonstration boards; a Web-based Resource Center; and system
design, online prototyping, and programming services.
We shipped our first FPGAs in 1988 and thousands of our
development tools are in the hands of customers, including BAE
Systems (BAE); The Boeing Company (Boeing); Cisco Systems, Inc.
(Cisco); European Aeronautic Defence and Space Company N.V.
(EADS); Hamilton Sundstrand; Honeywell International Inc.
(Honeywell); ITT Industries, Inc. (ITT); Lockheed Martin
Corporation (Lockheed Martin); Mitsubishi Corporation
(Mitsubishi); Nokia; Nortel Networks Corporation (Nortel);
Northrop Grumman Corporation (Northrop); Raytheon Company
(Raytheon); Rockwell Collins, Inc. and Rockwell Automation, Inc.
(Rockwell); Schlumberger Limited (Schlumberger); Siemens AG
(Siemens); Tellabs, Inc. (Tellabs); UTStarcom Incorporated
(UTStarcom); and Varian Medical Systems, Inc. (Varian).
We have foundry relationships with Chartered Semiconductor
Manufacturing Pte Ltd (Chartered) in Singapore; Infineon
Technologies AG (Infineon) in Germany; Matsushita Electric
Industrial Co., Ltd. (Matsushita) in Japan; United
Microelectronics Corporation (UMC) in Taiwan; and Winbond
Electronics Corp. (Winbond) in Taiwan. Wafers purchased from our
suppliers are assembled, tested, marked, and inspected by us
and/or our subcontractors before shipment to customers.
We market our products through a worldwide, multi-tiered sales
and distribution network. In 2004, sales made through
distributors accounted for 67% of our net revenues. One
distributor, Unique Technologies, Inc. (Unique), accounted for
33% of our net revenues in 2004. Unique has been our sole
distributor in North America since March 1, 2003. Including
Unique and about 15 sales representative firms, our North
American sales network has about 79 offices. Including about 21
distributors and sales representative firms, our European,
Pan-Asia, and Rest of World (ROW) sales network has about
58 offices. In 2004, sales to customers outside North America
accounted for 46% of net revenues.
On April 26, 2004, we announced the appointment of J.
Daniel McCranie to our Board of Directors. Mr. McCranie
brings more than 35 years of sales and marketing experience
in the semiconductor and communications industries to our Board
of Directors.
We were incorporated in California in 1985. Our principal
facilities and executive offices are located at 2061 Stierlin
Court, Mountain View, California 94043-4655, and our telephone
number at that address is (650) 318-4200. Our website is
located at http://www.actel.com. We provide access free
of charge through a link on our website to our Annual Reports on
Form 10-K, Quarterly Reports on Form 10-Q, and
Current Reports on Form 8-K, as well as amendments to those
reports, as soon as reasonably practicable after the reports are
electronically filed with or furnished to the Securities and
Exchange Commission (SEC). The Actel name and logo and Libero
are registered trademarks of Actel. This Annual Report also
includes unregistered trademarks of Actel as well as registered
and unregistered trademarks of other companies.
Industry Background
The three principal types of integrated circuits (ICs) used in
most digital electronic systems are microprocessor, memory, and
logic circuits. Microprocessors are used for control and
computing tasks; memory devices are used to store program
instructions and data; and logic devices are used to adapt these
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processing and storage capabilities to a specific application.
Logic circuits are found in practically every electronic system.
The logic design of competing electronic systems is often a
principal area of differentiation. Unlike the microprocessor and
memory markets, which are dominated by a relatively few standard
designs, the logic market is highly fragmented and includes,
among many other segments, low-capacity standard
transistor-transistor logic circuits (TTLs) and custom-designed
application specific ICs (ASICs). TTLs are standard logic
circuits that can be purchased “off the shelf” and
interconnected on a printed circuit board, but they tend to
limit system performance and increase system size and cost
compared with logic functions integrated at the circuit (rather
than the printed circuit board) level. ASICs are customized
circuits that offer electronic system manufacturers the benefits
of increased circuit integration: improved system performance,
reduced system size, and lower system cost.
ASICs include conventional gate arrays, standard cells, and
programmable logic devices (PLDs). Conventional gate arrays and
standard cell circuits are customized to perform desired logical
functions at the time the device is manufactured. Since they are
“hard wired” at the wafer foundry by use of masks,
conventional gate arrays and standard cell circuits are subject
to nonrecurring engineering (NRE) charges and the
time-to-market risks associated with any development cycle
involving a foundry. Typically, conventional gate arrays and
standard cell circuits are first delivered in production volumes
months after the successful production of acceptable prototypes.
In addition, hard-wired ASICs cannot be modified after they are
manufactured, which subjects them to the risk of inventory
obsolescence and constrains the system manufacturer’s
ability to change the logic design. PLDs, on the other hand, are
manufactured as standard devices and customized “in the
field” by electronic system manufacturers using
computer-aided engineering (CAE) design and programming
systems. PLDs are being used by a growing number of electronic
system manufacturers to increase product differentiation and
manufacturing flexibility and speed time to market.
PLDs include simple PLDs, complex PLDs (CPLDs), and FPGAs. CPLDs
and FPGAs have gained market share because they generally offer
greater capacity, lower total cost per usable logic gate and
lower power consumption than TTLs and simple PLDs, and faster
time to market and lower development costs than hard-wired
ASICs. As mask costs and NRE charges continue to rise, CPLDs and
particularly FPGAs are becoming cost-effective alternatives to
hard-wired ASICs at higher volumes. Even in high volumes, the
time-to-market and manufacturing-flexibility benefits of CPLDs
and FPGAs often outweigh their price premium over hard-wired
ASICs of comparable capacity for many electronic system
manufacturers.
Before a CPLD or FPGA can be programmed, there are various steps
that must be accomplished by a designer using CAE design
software. These steps include defining the function of the
circuit, verifying the design, and laying out the circuit.
Traditionally, logic functions were defined using schematic
capture software, which permits the designer to essentially
construct a circuit diagram on the computer. As CPLDs and FPGAs
have increased in capacity, the time required to create
schematic diagrams using schematic capture tools has often
become unacceptably long, so designers are increasingly turning
to hardware description languages (HDLs). HDLs permit the
designer to describe the circuit functions at an abstract level
and to verify the performance of logic functions at that level
using a simulator. The HDL description of the desired CPLD or
FPGA device can then be fed into synthesis software that
automatically converts the abstract description to a gate-level
representation equivalent to that produced by schematic capture
tools. After a gate-level representation of the logic function
has been created and verified, it must be translated or
“laid out” onto the generic logic modules of the CPLD
or FPGA. This is achieved by placing the logic gates and routing
their interconnections, a process referred to as “place and
route.” After the layout of the device has been verified by
timing simulation, the CPLD or FPGA can be programmed. Multiple
suppliers of electronic design automation (EDA) tools
provide software to accomplish the design entry, simulation, and
synthesis tasks for CPLDs and FPGAs, but the “place and
route” software is generally developed and provided only by
the CPLD or FPGA company.
Electronic system manufacturers program a CPLD or FPGA to
perform the desired logical functions by using a device
programmer to change the state of the device’s programming
elements (such as antifuses or memory cells) through the
application of an electrical signal. Programmers are typically
available from both
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the company supplying the device and third parties, and
programming services are often available from both the company
supplying the device and its distributors. Most CPLDs are
programmed with erasable programmable read only memories or
other nonvolatile “floating gate” memory technologies.
Many FPGAs are programmed with static random access memory
(SRAM) technology. Our FPGAs use Flash and antifuse
programming elements. After programming, the functionality and
performance of the programmed CPLD or FPGA in the electronic
system must be verified.
To a large extent, the characteristics of a CPLD or FPGA are
dictated by the technology used to make the device programmable.
CPLDs and FPGAs based on programming elements controlled by
floating gates or SRAMs must be configured by a separate boot
device, such as the nonvolatile programmable read only memory
(PROM) commonly used with SRAM FPGAs. Because these devices
must be booted-up, they are less reliable (in the sense of being
more prone to generate system errors), less secure, not
functional immediately on power-up, and require a separate boot
device. In addition, SRAM FPGAs and CPLDs based on look-up
tables tend to consume more power. FPGAs based on Flash and
antifuse programming elements do not need to be booted-up, which
makes them more reliable, more secure,
“live-at-power-up” single-chip solutions, and they
also tend to operate at lower power. These are all
characteristics shared by hard-wired ASICs but not by CPLDs or
SRAM FPGAs.
The technology used to make a CPLD or FPGA programmable also
dictates whether the device is reprogrammable and whether it is
volatile. CPLDs and FPGAs based on programming elements
controlled by floating gates or SRAMs are reprogrammable but
lose their circuit configuration in the absence of electrical
power. FPGAs based on antifuse programming elements are one-time
programmable and retain their circuit configuration permanently,
even in the absence of power. FPGAs based on programming
elements controlled by Flash memory are reprogrammable and
nonvolatile, retaining their circuit configuration in the
absence of power.
As mask and NRE costs for hard-wired ASICs continue to rise,
FPGAs are increasingly used as a cost-effective alternative to
ASICs for implementing complex design functions. With this
increase in adoption, FPGAs have grown in size and complexity,
making the security of the devices more important. More often
than not, the key IP that differentiates an electronic system
from competitive offerings is now implemented in programmable
logic. Consequently, the vulnerability of each system’s
unique value-added IP is often a direct function of the security
capabilities of the system’s FPGA. Since SRAM-based FPGAs
must be configured at power on, the bitstream used to configure
the SRAM FPGA can be intercepted in route at the circuit level,
electronically “captured,” and replicated.
Alternatively, this configuration data can be read from the
configuration device and manipulated or copied, or the on-board
PROM can be replicated. Flash and antifuse FPGAs do not require
a start-up bitstream, eliminating the possibility of
configuration data being intercepted.
SRAM FPGAs are also susceptible to being upset by neutrons and
alpha particles. When SRAM memories are used for data storage,
these neutron-induced errors are called “soft errors.”
When SRAM memories are used to store the configuration of an
FPGA, these neutron-induced errors are called “firm
errors.” A firm error affects the device’s
configuration, which may cause the device to malfunction. In
addition, firm errors are not transient but will persist until
detected and corrected. There is a significant and growing risk
of functional failure in SRAM-based FPGAs due to the corruption
of configuration data. Historically a concern only for military,
avionics, and space applications, firm errors have become more
of a problem for ground-based applications with each
manufacturing process generation. Radiation testing data show
that antifuse and Flash FPGAs are not subject to loss of
configuration due to neutron-induced upsets.
Strategy
Our Flash and antifuse technologies are different from, and have
certain advantages over, the SRAM and other technologies used in
competing PLDs. Our strategy is to offer innovative solutions to
markets in which our technologies have a competitive advantage,
including the value-based and high-reliability FPGA markets.
A general competitive advantage that our technologies have is
design security. Our nonvolatile, single-chip FPGAs offer
practically unbreakable design security. Decapping and stripping
of our Flash devices reveals only the structure of the Flash
cell, not the contents. Similarly, the antifuses that form the
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interconnections within our antifuse FPGAs do not leave a
signature that can be electrically probed or visually inspected.
In addition, special security fuses are hidden throughout the
fabric of our Flash and antifuse devices. These FlashLock and
FuseLock security fuses cannot be accessed or bypassed without
destroying the rest of the device, making both invasive and
noninvasive attacks ineffective.
Much of the logic market is driven by cost. We address this
value-based market, which we believe represents the fastest
growing segment of the FPGA market, with our Flash FPGAs and our
general-purpose antifuse FPGAs. In addition to low cost, our
FPGAs add the value of hard-wired ASICs to the benefits provided
by other PLDs. Like other PLDs, our FPGAs reduce design risk,
inventory investment, and time to market. Unlike other PLDs, our
FPGAs are nonvolatile, “live-at-power-up,” low-power,
single-chip solutions. In addition, logic designers can choose
to use either hard-wired ASIC or FPGA software tools and design
methodologies, and the architectures of our FPGAs enable the
utilization of predefined IP cores, which can be reused across
multiple designs or product versions. We also offer our
customers a wide selection of cost-sensitive and small
form-factor packages.
On March 29, 2004, we announced the shipment of the
one-millionth unit of our Flash-based ProASIC PLUS FPGA family,
which was introduced in 2002. With well over 1,000 design starts
worldwide, this product has the fastest customer acceptance rate
in our history, providing evidence that the nonvolatility and
reprogrammability of these single-chip devices, coupled with
their firm-error immunity, low power, and inherent security,
make them a cost-effective solution for the value-based FPGA
market. On January 24, 2005, we announced the ProASIC3 and
ProASIC3E FPGA families, which are targeted specifically at the
value-based FGPA market.
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High-Reliability Market |
Much of the logic market for military and aerospace applications
is driven by reliability, nonvolatility, security, and
resistance to radiation effects. We address this market with our
military, avionics, and space-grade FPGAs. Our antifuse and
Flash FPGAs are reliable, nonvolatile, secure, and not
susceptible to configuration corruption caused by radiation.
During 2004, we completed the introduction of our antifuse-based
RTAX-S FPGA family, with densities up to 2,000,000 gates, which
was designed specifically for space applications. The density
and performance characteristics of our RTAX-S FPGAs make them a
radiation-tolerant alternative to hard-wired ASICs in many
additional satellite applications. Much of the market for
automotive applications is driven by cost as well as
reliability, nonvolatility, and security. We address this market
with our automotive line of FPGAs. With the addition of the
Flash-based ProASIC PLUS devices to our automotive FPGA product
portfolio in 2004, we believe that we have the PLD
industry’s broadest automotive offering.
Products and Services
Our product line consists of FPGAs, including
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reprogrammable FPGAs based on Flash technology, |
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one-time programmable FPGAs based on antifuse
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high-reliability (HiRel) FPGAs. |
In 2004, FPGAs accounted for 96% of our net revenues, most of
which was derived from the sale of antifuse FPGAs. In support of
our FPGAs, we offer IP products; design and development
software; programming hardware; debugging tool kits and
demonstration boards; a Web-based Resource Center; and system
design, online prototyping, and volume programming services.
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FPGAs are used by manufacturers of automotive, communications,
computer, consumer, industrial, military and aerospace, and
other electronic systems to differentiate their products and get
them to market faster. We are the leading supplier of FPGAs
based on Flash and antifuse technologies.
To meet the diverse requirements of our customers, we offer all
of our FPGAs (except the two radiation-hardened devices) in a
variety of speed grades, package types, and/or ambient
(environmental) temperature tolerances. Commercial devices are
qualified to operate at ambient temperatures ranging from zero
degrees Celsius (0°C) to +70°C. Industrial devices are
qualified to operate at ambient temperatures ranging from
- -40°C to +85°C. Automotive devices are qualified to
operate at ambient temperatures ranging from -40°C to
+125°C with junction temperatures up to 125°C for
Flash devices and up to 150°C for antifuse devices.
Military devices are qualified to operate at ambient
temperatures ranging from -55°C to +125°C. “High
reliability” or “HiRel” devices are qualified to
automotive or military temperature specifications. We believe
that we are the leading supplier of high reliability FPGAs.
The capacity of FPGAs is measured in “gates,” which
traditionally meant four transistors. As FPGAs grew larger and
more complex, no standard technique emerged for counting FPGA
gates. The appearance of FPGAs with memory further complicated
matters because memory gates cannot be counted in the same way
as logic gates. When we use “gate” or
“gates” to describe the capacity of FPGAs, we mean
“maximum system equivalent gates” unless otherwise
indicated.
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Our Flash-based FPGAs include the ProASIC3, ProASIC3E, ProASIC
PLUS, and ProASIC families. The combination of a fine-grained,
single-chip ASIC-like architecture and nonvolatile Flash
configuration memory makes our Flash-based FPGAs economical
alternatives to ASICs for low- and medium-speed applications.
Unlike other FPGAs available on the market today, which are
either volatile or non-reprogrammable, our Flash devices are
nonvolatile and reprogrammable. |
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On January 24, 2005, we announced the ProASIC3 and
ProASIC3E families, our third generation of Flash-based
programmable logic solutions. The ProASIC3/E families were
designed to address the market demand for full-featured,
cost-effective FPGAs in consumer, automotive, and other
price-sensitive applications. Ranging in density from 30,000 to
3,000,000 gates, the new ProASIC3/E families offer integrated
secure in-system programmability (ISP) using Advanced
Encryption Standard (AES) encryption, 64-bit 66 MHz
Peripheral Component Interconnect (PCI) performance, and
the FPGA industry’s first on-chip user Flash memory. We
market the ProASIC3/E families as the world’s lowest cost
FPGAs. Samples are available through our early access program,
with production quantities scheduled for the end of 2005. |
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The ProASIC PLUS family of FPGAs, which was first shipped for
revenue in 2002, consists of seven devices: the 75,000-gate
APA075; the 150,000-gate APA150; the 300,000-gate APA300; the
450,000-gate APA450; the 600,000-gate APA600; the 750,000-gate
APA750; and the 1,000,000-gate APA1000. As our second-generation
Flash family, ProASIC PLUS devices offer added features and
improved user-configurable inputs and outputs (I/Os) and ISP
compared with the first-generation ProASIC family. Manufactured
on a 0.22-micron embedded Flash process at UMC, the ProASIC PLUS
family can be ordered in approximately 136 speed, package, and
temperature variations. |
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The ProASIC family of FPGAs, which was first shipped for revenue
in 1999, consists of four products: the 100,000-gate A500K050;
the 290,000-gate A500K130; the 370,000-gate A500K180; and the
475,000-gate A500K270. Manufactured on a 0.25-micron embedded
Flash process at Infineon, the family can be ordered in
approximately 30 speed, package, and temperature variations. |
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Our antifuse-based FPGAs include the Axcelerator, eX, SX-A, SX,
MX, and legacy families, all of which are nonvolatile, secure,
reliable, live at power-up, single-chip solutions. Our antifuse
FPGA devices span six process generations, with each offering
higher performance, lower power consumption, and improved
economies of scale. |
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The Axcelerator family of FPGAs, which was first shipped for
revenue in 2002, consists of five devices: the 125,000-gate
AX125; the 250,000-gate AX250; the 500,000-gate AX500; the
1,000,000-gate AX1000; and the 2,000,000-gate AX2000.
Manufactured on a 0.15-micron, seven-layer metal antifuse
process at UMC, the family can be ordered in approximately 204
speed, package, and temperature variations. The Axcelerator
family was targeted at high-speed communications and bridging
applications and designed to deliver high performance, logic
utilization, and design security with low power consumption. |
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The eX family of FPGAs, which was first shipped for revenue in
2001, consists of three devices: the 3,000-gate eX64; the
6,000-gate eX128; and the 12,000-gate eX256. Manufactured on a
0.25-micron antifuse process at UMC, the family can be ordered
in approximately 66 speed, package, and temperature variations.
The eX family was designed for the e-appliance market of
internet-related consumer electronics and includes a sleep mode
to conserve battery power. eX devices also provide a small form
factor, high design security, and a straightforward design
process. We market the eX family as high-performance single-chip
programmable replacements for low-capacity ASICs. |
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The SX-A family of FPGAs, which was first shipped for revenue in
1999, consists of four products: the 12,000-gate A54SX08A; the
24,000-gate A54SX16A; the 48,000-gate A54SX32A; and the
108,000-gate A54SX72A. Manufactured on a 0.22-micron antifuse
process at UMC and on a 0.25-micron antifuse process at
Matsushita, the family can be ordered in approximately 253
speed, package, and temperature variations. |
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The SX family of FPGAs, which was first shipped for revenue in
1998, consists of four products: the 12,000-gate A54SX08; the
24,000-gate A54SX16 and A54SX16P; and the 48,000-gate A54SX32.
Manufactured on a 0.35-micron antifuse process at Chartered, the
family can be ordered in approximately 200 speed, package, and
temperature variations. |
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SX was the first family to be built on our fine-grained,
“sea of modules” metal-to-metal architecture. We
market the SX-A and SX families as programmable devices with
ASIC-like speed, power consumption, and pricing in volume
production. In addition, the SX-A family offers I/ O
capabilities that provide full support for
“hot-swapping.” Hot swapping allows system boards to
be exchanged while systems are running, a capability important
to many portable, consumer, networking, telecommunication, and
fault-tolerant computing applications. |
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The MX family of FPGAs, which was first shipped for revenue in
1997, consists of six products: the 3,000-gate A40MX02; the
6,000-gate A40MX04; the 14,000-gate A42MX09; the 24,000-gate
A42MX16; the 36,000-gate A42MX24; and the 54,000-gate A42MX36.
Manufactured on 0.45-micron antifuse processes at Chartered and
Winbond, the family can be ordered in approximately 330 speed,
package, and temperature variations. We market the MX family as
a line of low-cost, single-chip, mixed-voltage programmable
ASICs for 5.0-volt applications. |
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The MX family incorporates the best features of our legacy FPGAs
and over time should replace those earlier products in new
5.0-volt commercial designs. Legacy products include the DX, XL,
ACT 3, ACT 2, and ACT 1 families. |
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The 3200DX family of FPGAs, which was first shipped for revenue
in 1995, consists of five products: the 12,000-gate A3265DX; the
20,000-gate A32100DX; the 24,000-gate A32140DX; the 36,000-gate
A32200DX; and the 52,000-gate A32300DX. Manufactured on a
0.6-micron antifuse process at Chartered, the family can be
ordered in approximately 171 speed, package, and temperature
variations. |
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The 1200XL family of FPGAs, which was first shipped for revenue
in 1995, consists of three products: the 6,000-gate A1225XL; the
9,000-gate A1240XL; and the 16,000-gate A1280XL. Manufactured on
a 0.6-micron antifuse process at Chartered, the family can be
ordered in approximately 126 speed, package, and temperature
variations. |
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The DX and XL families were designed to integrate system logic
previously implemented in multiple programmable logic circuits.
The DX family also offers fast dual-port SRAM, which is
typically used for high-speed buffering. |
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The ACT 3 family of FPGAs, which was first shipped for revenue
in 1993, consists of five products: the 3,000-gate A1415; the
6,000-gate A1425; the 9,000-gate A1440; the 11,000-gate A1460;
and the 20,000-gate A14100. Manufactured on a 0.6-micron
antifuse process at Chartered and a 0.8-micron antifuse process
at Winbond, the family can be ordered in approximately 189
speed, package, and temperature variations. The family was
designed for applications requiring high speed and a high number
of I/Os. |
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The ACT 2 family of FPGAs, which was first shipped for revenue
in 1991, consists of three products: the 6,000-gate A1225; the
9,000-gate A1240; and the 16,000-gate A1280. Manufactured on
1.0- and 0.9-micron antifuse processes at Matsushita, the family
can be ordered in approximately 73 speed, package, and
temperature variations. ACT 2 was our second-generation FPGA
family and featured a two-module architecture optimized for
combinatorial and sequential logic designs. |
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The ACT 1 family of FPGAs, which was first shipped for revenue
in 1988, consists of two products: the 2,000-gate A1010 and the
4,000-gate A1020. Manufactured on 1.0- and 0.9-micron antifuse
processes at Matsushita, the family can be ordered in
approximately 95 speed, package, and temperature variations. ACT
1 was the original family of antifuse FPGAs. |
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Our HiRel FPGAs include automotive products, which are offered
in plastic packages; military/avionics (Mil/Av) products, which
are offered in plastic or ceramic (hermetic) packages; and
radiation tolerant (Rad Tolerant) and radiation hardened (Rad
Hard) products, which are offered in hermetic packages. We
believe that we are the leading supplier of high reliability
FPGAs. Our FPGAs have been designed into numerous military and
aerospace applications, including command and data handling,
attitude reference and control, communication payload, and
scientific instrument interfaces. Our space-qualified FPGAs have
been on board more than 100 launches and accepted for
flight-unit applications on more than 300 satellites. |
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To address the rapidly growing and cost-sensitive automotive
electronics market, we introduced in 2003 an automotive line of
FPGAs covering a wide range of densities, voltages, and
features. We offer extended automotive temperature versions of
all members of our eX, SX-A, and MX antifuse families. On
February 9, 2004, we announced the availability of our
Flash-based ProASIC PLUS FPGAs, with densities up to 1,000,000
gates, in extended automotive temperature range versions. Our
ProASIC PLUS automotive devices are suitable for telematics and
other in-cab applications that require flexible,
high-reliability solutions, including navigation, speech
recognition, passenger control and comfort systems, intelligent
occupant sensors, and heads-up displays. Due to the
tamper-resistant nature of our Flash and antifuse technologies,
our automotive line is also appropriate for occupant safety
systems, electronic engine control modules, and other
under-the-hood powertrain management systems. We market our
automotive line as the FPGA industry’s broadest automotive
product portfolio that addresses the unique needs of vehicle
designers. |
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Our Mil/Av devices are offered in three packaging and screening
options: military-temperature plastic (MTP),
military-temperature hermetic (MTH), and MIL-STD 883
Class B hermetic (Class B). MTP devices are offered in
plastic packages and screened to military temperature
specifications. MTH devices are offered in hermetic packages and
screened to military temperature specifications. Class B
devices are offered in hermetic packages and screened to MIL-STD
883 Class B specifications. |
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All members of our antifuse FPGAs families (except for the AX125
and the three eX devices) are offered in MTP packaging and
screening. We have received complete Qualified Manufacturers
Listing (QML) certification for the full line of MTP
antifuse FPGAs, which can be integrated into design applications
that would otherwise require higher-cost ceramic-packaged
devices. The QML plastic certification also permits customers to
integrate commercial and military production without
compromising quality or reliability. |
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We offer 22 devices in MTH or Class B packaging and
screening: the 2,000-gate A1010B; the 4,000-gate A1020B; the
6,000-gate A1425A; the 9,000-gate A1240A; the 11,000-gate
A1460A; the 16,000-gate A1280A and A1280XL; the 20,000-gate
A14100A and A32100DX; the 24,000-gate A54SX16; the 36,000-gate
A32200DX; the 48,000-gate A54SX32 and A54SX32A; the 54,000-gate
A42MX36; the 108,000-gate A54SX72A; the 250,000-gate AX250; the
300,000-gate APA300; the 500,000-gate AX500; the 600,000-gate
APA600; the 1,000,000-gate APA1000 and AX1000; and the
2,000,000-gate AX2000. Hermetic-packaged Mil/ Av devices are
appropriate for avionics, munitions, harsh industrial
environments, and ground-based equipment when radiation
survivability is not critical. |
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On February 11, 2004, we announced the introduction of the
RTAX250S FPGA, extending our RTAX-S family to three devices. On
July 6, 2004, we announced the availability of engineering
samples for all three devices, which have features optimized for
space applications, including hardened registers that offer
practical immunity to single-event upsets and usable
error-corrected onboard random access memory (RAM). We believe
that these features, in combination with proven reliability at
extreme temperatures, live-at-power-up functionality on a single
chip, and an expanded set of I/O standards, enable the RTAX-S
family to meet the density, performance, and
radiation-resistance requirements of many satellite bus and
payload applications, including command and data handling,
attitude and orbit control, and spacecraft power and
environmental controls. We market the RTAX-S family as a
radiation-tolerant alternative to hard-wired ASICs for bus and
payload applications in low-, mid-, and geosynchronous-earth
orbit satellites. |
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On June 21, 2004, we announced the availability of our
radiation-tolerant RTSX-S family of FPGAs from UMC’s wafer
foundry. The new family provided customers with an alternate
source for |
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our 0.25-micron devices, which have been widely adopted for
radiation-intensive space-flight applications. To help assure
that the devices from UMC meet the stringent requirements of
space-flight systems, the parts have been subjected to numerous
qualification, reliability, and radiation tests. See the Risk
Factors set forth at the end of Item 1 of this Annual
Report on Form 10-K for more information. |
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Our Rad Tolerant family of FPGAs consists of ten products: the
4,000-gate RT1020; the 6,000-gate RT1425A; the 11,000-gate
RT1460A; the 16,000-gate RT1280A; the 20,000-gate RT14100A; the
48,000-gate RT54SX32S; the 108,000-gate RT54SX72S; the
250,000-gate RTAX250S; the 1,000,000-gate RTAX1000S; and the
2,000,000-gate RTAX2000S. These Rad Tolerant FPGAs are offered
with Class B or Class E (extended flow/space)
qualification and total dose radiation test reports are provided
on each segregated lot of devices. The RT54SX32S is also offered
in a chip carrier land grid package small enough to enable the
assembly of tested and programmed FPGAs into multi-chip modules
for space applications. |
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Rad Tolerant FPGAs are designed to meet the logic requirements
for all types of military, commercial, and civilian space
applications, including satellites, launch vehicles, and
deep-space probes. They provide cost-effective alternatives to
radiation-hardened devices when radiation survivability is
important but not essential. In addition, Rad Tolerant devices
have design- and pin-compatible commercial versions for
prototyping. |
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The Rad Hard family of FPGAs, which was first shipped for
revenue in 1996, consists of two products: the 4,000-gate RH1020
and the 16,000-gate RH1280. The two products were manufactured
on a radiation-hardened 0.8-micron antifuse process by BAE and
are shipped with full QML Class V screening. The Rad Hard
family was designed to meet the demands of applications
requiring guaranteed levels of radiation survivability. Rad Hard
FPGAs are appropriate for military and civilian satellites, deep
space probes, planetary missions, and other applications in
which radiation survivability is essential. |
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Supporting Products and Services |
In support of our FPGAs, we offer IP products; design and
development software; programming hardware; debugging tool kits
and demonstration boards; a Web-based Resource Center; and
system design, online prototyping, and volume programming
services.
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IP products allow system designers to leverage proven, pre-built
IP cores optimized for our devices, which streamlines their
design process, shortens time to market, and reduces design cost
and risk. Targeting the aerospace, automotive, communications,
consumer, industrial, and military markets, our IP cores
complement the nonvolatile, secure, and low-power
characteristics of our Flash and antifuse FPGAs. Our offering
includes approximately 34 bus interface, 23 communications, 12
data security, five memory control, 16 multimedia and error
correction, and 27 processor and peripheral IP cores. The IP
cores are available in evaluation, register transfer language
(RTL), or netlist formats. |
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Data security is an integral part of our leading solutions for
secure semiconductor devices. We have industry-standard data
encryption IP cores and partnerships that meet the stringent
needs of the security marketplace. Our security IP portfolio
includes Data Encryption Standard (DES), Triple DES, and AES
cores designed and targeted to work with our Flash and antifuse
FPGAs. We are partnering with experts in the area of data
security who offer their services to integrate these cores into
our devices. |
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On January 24, 2005, we announced the availability of more
than 90 IP cores to support our new ProASIC3 and ProASIC3E
device families. The ported cores leverage the advanced features
of the ProASIC3/E devices, including enhanced I/O and memory.
Delivering a broad IP library at the time of |
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product introduction allows our customers to begin designing
complete systems with the ProASIC3/ E devices. |
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We design, verify, support, and maintain DirectCore IP products,
which are optimized for use with our devices. These cores come
complete as pre-implemented, synthesizable building blocks that
have been thoroughly tested and verified in our FPGAs. A number
of them are certified for operation to a standard, such as PCI
or MIL-STD-1553. Approximately 23 DirectCore IP cores are
available from us or through our distributors or sales
representatives. We offer evaluation, single-use, and
unlimited-use licenses for our IP cores, which are delivered
with full documentation and support. On October 25, 2004,
we announced a new Web-based IP evaluation program that allows
customers to access and download free evaluation versions of
DirectCore IP products from our Web site. |
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Our CompanionCore Alliance Program is a cooperative effort
between us and independent third-party IP core developers to
produce and provide a wide selection of proven, pre-built
synthesizable semiconductor IP cores optimized for use in our
FPGAs and compatible with our suite of design and development
tools. These CompanionCore IP cores are licensed, supported, and
maintained directly by the partners. |
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On February 9, 2004, we announced that a new CompanionCore
Alliance Program partner, Intelliga Integrated Design, had
optimized its local interconnect network and controller area
network (CAN) cores to support our automotive- and
industrial-temperature grade devices. We now offer more than 30
IP cores specifically designed and optimized for in-cab and
under-the-hood automotive applications. |
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Approximately 92 CompanionCore IP cores are available from our
CompanionCore Alliance Program partners, including ten from 4i2i
Communications Ltd; six from CAST, Inc.; five from Eureka
Technology Inc.; nine from Helion Technology Ltd.; two from
Intelliga Integrated Design; 26 from Inicore, Inc. (Inicore); 25
from Memec Design; and nine from MorethanIP GmbH. A number of
licensing models are available from our CompanionCore Alliance
partners, including single-use, multiple-use, and evaluation
licenses. |
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• |
Design and Development Software |
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Our software strategy is to provide our customers with all of
the tools necessary for them to define, verify, and implement
their designs in our FPGAs by combining tools from leading EDA
vendors with our custom developed tools into a single FPGA
integrated design environment (IDE). We also work closely with
our EDA partners to ensure that new releases of our custom
developed tools are supported in their software and design
flows. Our EDA partners include Aldec, Inc.; Cadence Design
Systems, Inc. (Cadence); Celoxica Limited; Magma Design
Automation, Inc. (Magma); Mentor Graphics Corporation (Mentor
Graphics); SynaptiCAD, Inc. (SynaptiCAD); Synopsys, Inc.
(Synopsys); and Synplicity, Inc. (Synplicity). |
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Our Libero IDE is a comprehensive FPGA design and development
software suite that supports all of our Flash and antifuse FPGA
families and provides users with start-to-finish design flow
guidance and control. The Libero IDE provides complete tool
interoperability; a streamlined design flow; management of all
design, run, and log files; seamless passing of all design data
between tools from schematic/HDL entry through place-and-route;
and device programming. The entire design can be created and
managed through the Libero IDE’s user interface, which
provides a step-by-step graphical illustration of the design
flow process. |
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Running on Microsoft Windows operating systems, the Libero IDE
is available in several editions. The Libero IDE Silver edition,
which we offer for free, contains our Designer physical |
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design implementation tool suite and a project manager as well
as Actel Edition (AE) versions of the following third party
tools: Mentor Graphics’ ViewDraw AE schematic capture;
SynaptiCAD’s Waveformer Lite AE testbench generator; and
Synplicity’s Synplify AE synthesis tools. The Libero IDE
Gold edition also includes Mentor Graphics’ ModelSim AE
simulator. The Libero IDE Silver and Gold editions support our
FPGAs through 300,000 gates as well as the new A3PE600 ProASIC3E
device. The most comprehensive edition, Libero IDE Platinum,
also includes Magma’s PALACE AE physical synthesis tools
and supports all of our currently released devices. |
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On January 24, 2005, we announced that our Libero 6.1 IDE
provides complete support for our new Flash-based ProASIC3 and
ProASIC3E devices. The software is optimized for the
architectural features of the ProASIC3 and ProASIC3E devices,
including the on-chip FlashROM, which can be programmed
independently of the FPGA core. In addition, the Libero 6.1 IDE
includes Synplicity’s Synplify Pro AE, which offers many
features beyond Synplify AE to improve device performance and
design time. Synplify Pro AE requires a separate license and can
be used with any Libero IDE edition. |
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For customers who want to us their own design and verification
tools, our Designer software is available as a standalone
interactive design implementation tool suite. It is compatible
with the most popular design entry and verification packages,
including those from Cadence, Mentor Graphics, Synopsys, and
Synplicity. The Designer software includes all of the tools
required for a complete physical design implementation system,
from importing a netlist through place-and-route, timing and
physical constraints entry, timing and power analysis, and
programming file generation. In addition to a step-by-step
design flow, the tool suite also provides access to many
features that streamline or facilitate completion of the design,
including floorplanning tools. Running on Microsoft Windows, Sun
Solaris, or Red Hat Linux operating systems, the Designer
software is offered in a Platinum edition that supports all of
our devices, including the new ProASIC3/ E Flash families, and a
free Gold edition that supports all devices up to 300,000 gates
as well as the smallest member of each family. |
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Programmers execute instructions included in files obtained from
the Designer tool suite to program our FPGAs. In addition to
programmers, we offer adapter modules, which must be used with
the Silicon Sculptor II programmer; surface-mount sockets
and prototyping adapter boards, which make it easier to
prototype designs using our antifuse FPGAs; and accessories. In
addition, we support programmers offered by BP Microsystems, Inc. |
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All of our FPGAs can be programmed by the Silicon
Sculptor II programmer. The Silicon Sculptor II
programmer is a compact, single-device programmer with
stand-alone software for the personal computer (PC). Silicon
Sculptor II was designed to allow concurrent programming of
multiple units from the same PC. The Silicon Sculptor II is
manufactured for us by BP Microsystems. |
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Our family of FlashPro device programmers provides ISP support
for the ProASIC3/E, ProASIC PLUS, and ProASIC FPGA families. The
ISP feature permits devices to be programmed after they are
mounted on a printed circuit board. Running on Microsoft Windows
operating systems, all FlashPro programmers permit multiple
Flash devices to be programmed in a Joint Test Action Group
(JTAG) chain. Since any nonprogrammable devices in the JTAG
chain are automatically skipped, a single JTAG chain can be used
for all JTAG devices, which increases flexibility for
post-production and field upgrades. All FlashPro programmers
also use industry-standard test and programming language files,
so there is no delay between product release and |
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programming support. In addition, the same graphical user
interface (GUI) is used for all FlashPro series
programmers, which are manufactured for us by First Silicon
Solutions, Inc. (FS2). |
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The FlashPro3 programmer is targeted at the ProASIC3 and
ProASIC3E families, our latest generation of Flash devices. This
newest programmer offers high-speed performance through the use
of Universal Serial Bus (USB) 2.0 and is compliant for full
use of the 480 Mbps bandwidth. The FlashPro3 programmer can
connect to any PC with a USB port and can operate either with
USB 1.1 (full-speed) or USB 2.0 (both high-speed and full-speed
modes). By using USB hubs, multiple FlashPro3 programmers can be
connected to a single PC, enabling the end-user to set up a
small-scale production environment with concurrent ISP occurring
across multiple boards. |
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The FlashPro Lite programmer is used exclusively with the
ProASIC PLUS family and connects to a PC by means of the
parallel port. A replaceable programming cable connects the
FlashPro Lite to the target board, which powers the programmer.
This portable, low-cost programmer permits customers to program
ProASIC PLUS devices at almost any location using a laptop
computer. |
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The FlashPro programmer can be used with both the ProASIC PLUS
and Pro ASIC families. The choice of USB port or parallel port
is made in the FlashPro software GUI. The FlashPro programmer
has its own power supply, so the target board does not need to
be powered up to support ISP. Like FlashPro3 programmers,
multiple FlashPro programmers can be connected by USB hubs to a
single PC. |
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• |
Debugging Tool Kits and Demonstration Boards |
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Our design diagnostics and debugging tool kits and accessories
permit designers to improve productivity and reduce time to
market by removing the guesswork typically associated with the
process of system verification. We offer different tools kits
for our Flash and antifuse products. Our development kits and
demonstration boards and accessories permit users to evaluate
particular products. |
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Design Diagnostics and Debugging Tool Kits |
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Our antifuse FPGAs contain internal circuitry that provides
built-in access to every node in a design, enabling real-time
observation and analysis of a device’s internal logic
nodes. Silicon Explorer II is an integrated verification
and logic analysis tool kit for the PC that accesses the probe
circuitry. Silicon Explorer II Lite is a less expensive
version of Silicon Explorer II for customers who have a
logic analysis system. |
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The FS2 CLAM (Configurable Logic Analyzer Module) System
provides logic analyzer capabilities for our Flash-based FPGAs.
Embedded in our Flash devices, the CLAM System can
simultaneously trace and trigger on up to 256 channels from an
available 1024 predefined signals in the FPGA. The FS2 CLAM
hardware probe is offered by FS2. |
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Development Kits and Demonstration Boards |
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On November 1, 2004, we announced the availability of a
starter kit for our antifuse-based Axcelerator FPGA. Available
in both a basic evaluation and an advanced prototyping version,
the starter kit features an evaluation board with an Axcelerator
device, the Libero Gold IDE, tutorials, and support
documentation. In addition, users can submit custom Axcelerator
designs and receive free, programmed samples through our new
Online Prototyping Service. The advanced prototyping kit
includes a programming socket module adapter and a six-month
loaner program certificate for our Silicon Sculptor II
programmer. |
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During 2004, we also announced the availability of an enhanced
starter kit for our Flash-based ProASIC PLUS FPGAs. In addition,
we offer ProASIC PLUS and Axcelerator evaluation platforms; a
ProASIC PLUS ISP demonstration evaluation platform; CorePCI,
Core1553, and CorePCIX evaluation boards; and Core1553BRM, Core
429, and Platform8051 development kits. |
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On January 24, 2005, we announced a starter kit to support
our new Flash-based ProASIC3 and ProASIC3E FPGA families.
Expected to be available in the second quarter of 2005, the
starter kit includes an evaluation board with a ProASIC3E
device, the Libero Gold 6.1 IDE, a FlashPro3 programmer, USB
cable, programming cable, power supply, tutorials, and support
documentation. |
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Launched in 2002, our Web-based Resource Center is intended to
provide information on a variety of industry-wide issues related
to the continued displacement of hard-wired ASICs by FPGAs.
Targeted at FPGA and ASIC designers and system architects, the
website includes technology tutorials, frequently-asked
questions, market overviews, application notes, white papers,
extensive glossaries of industry terms, and links to other
relevant articles and third-party resources. Additional topics
will be added as appropriate. |
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The Power Resource Center provides design engineers with
information about the power characteristics of FPGAs as well as
tools to estimate and design for low-power applications. The
four basic power components that need to be examined when
evaluating the power consumption of different FPGA technologies
are static power, dynamic power, in-rush (or power-up) power,
and configuration power. While the three primary FPGA
technologies differ widely in their power consumption
characteristics, only Flash and antifuse are (like ASICs) true
live-at-power-up technologies that do not exhibit power-up
current spikes. |
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Our Packaging Resource Center contains technical package
details, discussions on the latest environmental issues, related
industry articles and links, and design implementation tools.
This portal was created as the primary source for technical
information about our FPGA packaging solutions, but also serves
as an industry reference for IC packaging issues and topics that
impact the FPGA design community. Our objective is to
consistently deliver packages that provide the necessary
mechanical and environmental protection to ensure consistent
reliability and performance. On March 22, 2004, we
announced the availability of “green” and lead-free
packaging options for all of our antifuse- and Flash-based FPGA
product families. |
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On April 19, 2004, we announced the results of a
comprehensive third-party investigation verifying that FPGAs
based on Flash and antifuse technologies are immune to
configuration upsets caused by high-energy neutrons naturally
generated in the earth’s atmosphere. The study also
determined that SRAM-based FPGAs are vulnerable to
neutron-induced configuration loss not only under high-altitude
conditions, as traditionally believed, but also in ground-based
applications, including automotive, medical, telecommunications,
data storage, and communications. A neutron-induced functional
failure in an SRAM-based FPGA can result in a complete system
failure. The tests followed the industry-prescribed test
methodology and were conducted at the Los Alamos National
Laboratory in New Mexico. The results of the independent study
are documented in a report (“Radiation Results of SER
[Soft-Error Rate] Test of Actel, Xilinx, and Altera FPGA
Instances”) that is available in our Soft/ Firm Errors
Resource Center. This website also contains technology
tutorials, white papers, a comprehensive glossary, and relevant
links. |
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• |
Embedded Design Security |
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Secure systems and ultimately the underlying silicon
technologies are becoming increasingly vital in protecting
valuable IP. Without taking the necessary precautions,
corporations may experience major security breaches, resulting
in design theft and other malicious damage. But assessing
security risks and the potential associated loss can be
difficult. The purpose of our Embedded Design Security Resource
Center is to provide semiconductor and design professionals with
a database of information about these vulnerabilities.
Organizations concerned with security can now access detailed
information and links about design security, security
countermeasures, affected systems, and solutions to defeat
unfriendly attacks. Our solution is a range of nonvolatile,
single-chip FPGAs that offer practically unbreakable design
security. |
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In addition to the system design, online protyping, and volume
programming services that we offer, our Solution Partners
Program provides customers with access to a broad range of
design resources, application expertise, and products from
strategic partners worldwide that complement our products and
services. |
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Protocol Design Services |
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With our acquisition of the Protocol Design Services Group from
GateField Corporation (GateField) in August 1998, we became the
first FPGA provider to offer system-level design expertise. The
Design Services organization operates out of a secure facility
located in Mt. Arlington, New Jersey, and is certified to handle
government, military, and proprietary designs. The organization
provides varying levels of design services to customers,
including FPGA, ASIC, and system design; software development
and implementation; and development of prototypes, first
articles, and production units. Our Protocol Design Services
team has participated in the development of a wide range of
applications, including optical networks, routers, cellular
phones, digital cameras, embedded DSP systems, automotive
electronics, navigation systems, compilers, custom processors,
and avionics systems. |
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On November 1, 2004, we announced our new Online Protoyping
Service, a Web-based sample delivery program. Intended to make
it easy for designers to evaluate and prototype with no up-front
investment, the new program allows them to request free samples
of programmed FPGAs through a Web-based interface. The program
currently supports our antifuse-based Axcelerator, SX-A, eX and
MX families. |
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We offer high-volume programming for all device and package
types in our programming center, which is located at our factory
in Mountain View, California. Our facility is ISO 9001:2000,
PURE, QML, and STACK certified (see “BUSINESS —
Manufacturing and Assembly). As part of the programming process,
we offer ink marking for customer-specific marking needs. Volume
programming charges are based on the type of device and quantity
per order. |
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On July 12, 2004, we announced the addition of five new
members to our Solution Partners Program, which is a cooperative
effort between us and third-party providers of FPGA design
services, embedded software, and hardware products. The Solution
Partners Program is intended to help accelerate the time to
market for designs based on our devices by enabling designers to
leverage FPGA design expertise and products tailored
specifically for our devices. Solution Partner products and
services are available directly from the partners, who are
responsible for pricing, warranty, and technical support.
Joining the Program were Barco-Silex, Capitol Automation, Comit
Systems, Intrinsix Corporation, and Silicon Interfaces, all of
whom develop customer-specific electronic |
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products for the wired and wireless communications and
networking markets. On February 14, 2005, we announced that
four more new partners had joined the Solution Partners Program:
Altium Limited, Data I/O Corporation, Device Engineering Inc.,
and GAO Research Inc. The Program currently has 22 members. |
Markets and Applications
FPGAs can be used in a broad range of applications across nearly
all electronic system market segments. Most customers use FPGAs
in low to medium volumes in the final production form of their
products. Some high-volume electronic system manufacturers use
FPGAs as a prototyping vehicle and convert production to
lower-cost hard-wired ASICs, while others with time-to-market
constraints use FPGAs in the initial production and then convert
to lower-cost ASICs. For electronic systems that have shortened
product life cycles, system manufacturers are finding that the
cost difference between hard-wired ASICs and FPGAs begins to
shrink and that manufacturing flexibility becomes a more
important element in the semiconductor decision process. In
addition, as new chip interface standards emerge (which also
puts a premium on flexibility), more high-volume electronic
system manufacturers are electing to retain FPGAs in volume
production.
In 2004, military and aerospace applications accounted for an
estimated 36% of our net revenues. Rigorous quality and
reliability standards and the need for design security are the
primary product characteristics of the military and aerospace
market. Our FPGAs have high quality and reliability and are
almost impossible to copy or reverse engineer, making them
appropriate for many military and aerospace applications. We
believe that we are the world’s leading supplier of
military and aerospace PLDs. Our customers in the military and
aerospace market include: BAE, Boeing, EADS, Hamilton
Sundstrand, Honeywell, ITT, Lockheed Martin, Northrop, Raytheon,
and Rockwell.
Our antifuse FPGAs are especially well suited for space
applications due to the high radiation tolerance of the antifuse
and our FPGA architecture. Thousands of our FPGAs have performed
flight-critical functions aboard manned space vehicles, earth
observation satellites,