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UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549

FORM 10-K

OR

For the transition period from                              to                             

Commission File Number: 000-22671

QUICKLOGIC CORPORATION
(Exact name of registrant as specified in its charter)

1277 Orleans Drive
Sunnyvale, CA 94089
(Address of principal executive offices, including zip code)

Registrant's telephone number, including area code: (408) 990-4000

Securities registered pursuant to Section 12(b) of the Act: None

Securities registered pursuant to Section 12(g) of the Act: Common Stock, $0.001 par value

(Title of Class)

        Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes /x/ No / /

        Indicate by check mark if disclosure of delinquent filers pursuant to item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. / /

        The aggregate market value of voting stock held by non-affiliates of the registrant as of February 27, 2002 was $63,679,267 based upon the last sales price reported for such date on The Nasdaq National Market. For purposes of this disclosure, shares of common stock held by persons who hold more than 5% of the outstanding shares of common stock and shares held by officers and directors of the registrant, have been excluded in that such persons may be deemed to be affiliates. This determination is not necessarily conclusive.

        At February 27, 2002 Registrant had outstanding 23,185,808 shares of Common Stock.

DOCUMENTS INCORPORATED BY REFERENCE

        The Registrant has incorporated by reference into Part III of this Form 10-K portions of its Proxy Statement for Registrant's Annual Meeting of Stockholders to be held on or about April 23, 2002.

EXPLANATORY NOTE

        Statements in this Business section, and elsewhere in this Annual Report on Form 10-K, which express that the Company "believes", "anticipates" or "plans to....", as well as other statements which are not historical fact, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Actual events or results may differ materially as a result of the risks and uncertainties described herein and elsewhere including, in particular, those factors described under "Management's Discussion and Analysis of Financial Condition and Results of Operations" and "Factors Affecting Future Results."

PART I

ITEM 1. BUSINESS

Overview

        QuickLogic Corporation develops, markets and supports advanced field programmable gate array, or FPGA, and embedded standard product, or ESP, semiconductors and the software tools that enable design engineers to use our products. We introduced ESPs, a new class of semiconductor devices, in 1998, to address the design community's demand for a solution that bridges the gap between existing application specific integrated circuit, or ASIC, options and the long-sought goal of system-on-a-chip. Specifically, our ESP devices provide engineers with the ease-of-use, guaranteed functionality and high-performance of standard products, combined with the flexibility of programmable logic. Our ESP and FPGA products target complex, high-performance systems in rapidly changing markets where system manufacturers seek to minimize time-to-market and maximize product differentiation and functionality. We compete in various markets, including telecommunications and data communications; video/audio, graphics and imaging; instrumentation and test; high-performance computing; and military systems.

        In August 2001, we completed the acquisition of certain assets of V3 Semiconductor, Inc. ("V3"), a manufacturer of application specific standard products, or ASSPs. The acquisition of V3 provides us with a design center in Canada and additional ASSP products that complement certain of our ESP products.

Product Technology

        The key components of our ESP and FPGA product families are our ViaLink programmable metal technology, our user-programmable platform and the associated software tools used for product design. Our ViaLink technology allows us to create smaller devices than competitors' comparable products, thereby minimizing silicon area and cost. In addition, our ViaLink technology has lower electrical resistance and capacitance than other programmable technologies and, consequently, supports higher signal speed. Our user-programmable platform facilitates full utilization of a device's logic cells and Input/Output pins. These logic cells have been optimized to efficiently implement a wide range of logic functions at high speed, thereby enabling greater usable device density and design flexibility. Our architecture uses our ViaLink technology to maximize interconnects at every routing wire intersection. The abundance of interconnect resources allows more paths between logic cells. As a consequence, system designers are able to use QuickLogic devices with smaller gate counts than competing FPGAs to implement their designs. These smaller gate-count devices require less silicon area and as a result are able to be offered at a lower price. Finally, our software enables our customers to efficiently implement their designs using our products.

Industry Background

        Competitive pressures are forcing manufacturers of electronic systems to rapidly bring to market products with improved functionality, higher performance and greater reliability, all at lower cost.

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Providers of systems requiring high-speed data transmission and processing such as communications equipment, digital image products, test and instrumentation and storage subsystems face intense time-to-market pressures. These market forces have driven the evolution of logic semiconductors, which are used in complex electronic systems to coordinate the functions of other semiconductors, such as microprocessors or memory. There are three types of advanced logic semiconductors:

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Application specific integrated circuits, or ASICs, are special purpose devices designed for a particular manufacturer's electronic system. These devices are customized during wafer manufacturing;



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Application specific standard products, or ASSPs, are fixed-function devices designed to comply with industry standards that can be used by a variety of electronic systems manufacturers. Their functions are fixed prior to wafer fabrication; and



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Programmable logic devices, or PLDs, are general-purpose devices which can be used by a variety of electronic systems manufacturers, and are customized after purchase for a specific application. Field programmable gate arrays, or FPGAs, are types of PLDs used for complex functions.

        Systems manufacturers have relied heavily on ASICs to implement the advanced logic required for their products. ASICs provide high performance due to customized circuit design. However, because ASICs are design-specific devices, they require long development and manufacturing cycles, delaying product introductions. In addition, because of the expense associated with the design of ASICs, they are cost effective only if they can be manufactured in high volumes. Finally, once ASICs are manufactured, their functionality cannot be changed to respond to evolving market demands.

        ASSPs have become widely utilized as industry standards have developed to address increasing system complexity and the need for communication between systems and system components. These standards include:

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Peripheral component interconnect, or PCI, a standard developed to provide a high performance, reliable and cost-effective method of connecting high-speed devices within a system;



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Synchronous optical network, or SONET, a fiber-optic transmission standard for high-speed digital traffic, employed mainly by telephone companies and other network service providers;



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Ethernet, a widely-used local area network, or LAN, transport standard which controls the interconnection between servers and computers; and



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Fibre channel interconnect protocol, an industry networking standard for storage area networks, or SANs, which controls the interconnection between servers and storage devices.

        Compared to ASICs, ASSPs offer the systems designer shorter development time, lower risk and reduced development cost. However, ASSPs generally cannot be used by systems manufacturers to differentiate their products. To address markets where industry standards do not exist or are changing and time-to-market is important, PLDs are often used. These products provide systems manufacturers with the flexibility to customize and thereby differentiate their systems, unlike ASSPs. PLDs also enable systems manufacturers to change the logic functionality of their systems after product introduction without the expense and time of redesigning an ASIC. However, most PLDs are more expensive than ASSPs and even ASICs of equivalent functionality because they require more silicon area. In addition, most PLDs offer lower performance than nonprogrammable solutions, such as ASSPs and ASICs.

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Industry Future: System-on-a-Chip

        Over the past few years, semiconductor manufacturers have migrated to smaller process geometries. These smaller process geometries enable more logic elements to be incorporated in a single chip using less silicon area. More recently, advances have been made in the integration of logic and memory on a single chip, which had been difficult previously due to incompatible process technologies. The industry "holy grail" is to have the three basic components of all electronic circuit boards; logic, memory and a microprocessor, on the same chip. Advantages of the single-chip approach to systems manufacturers include:

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simplified system development;



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reduced time-to-market;



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elimination of delays associated with the transfer of data between chips;



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smaller physical size;



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lower power dissipation;



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greater reliability; and



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lower cost.

        However, as levels of logic integration have increased, devices have become more specific to a particular application. This fact limits their use and potential market size.

QuickLogic's ESP Solution

        QuickLogic has leveraged its unique ViaLink technology and user-programmable platform to address the limitations inherent in current system-on-a-chip approaches. The result is embedded standard products, or ESPs, that deliver the advantages offered by both FPGAs and ASSPs. In its simplest form, an ESP contains four basic parts: a programmable logic array, an embedded standard function, an optional programmable read-only memory to configure the embedded function, and an interface that allows communication between the standard function and programmable logic array. Our ESP products combine the system-level functionality of ASSPs with the flexibility of FPGAs. We believe ESPs offer the following specific advantages:

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Increased Performance. In a typical design, data must travel between an ASSP and an FPGA across a printed circuit board. The limited number of connections available and the distance between the devices can degrade the system's overall performance. Our ESP solution allows all data to be processed on a single chip;



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Decreased Cost. Because our ESP is a single chip solution, it requires less silicon area, and therefore is less expensive to produce. Additionally, this single chip approach lowers the component, assembly and test cost for the system manufacturer;



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Increased Reliability. ESP designs are more reliable because single chip solutions contain fewer components and circuit board connections that are subject to failure; and



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Shorter Development Time. With a multiple chip design, systems designers must solve complex routing and timing issues between devices. A single chip ESP solution eliminates the timing issues between devices and simplifies software simulation, leading to shorter development time.

        We have introduced six ESP product lines since 1998. These include the QuickSD, QuickFC and QuickPCI families—products aimed at the high-speed interconnect section of the fast-growing communications market. In addition we have introduced QuickDSP and QuickRAM, for high-performance Digital Signal Processing, or DSP, applications and applications that require

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embedded memory. Most recently we have introduced our QuickMIPS family to serve applications that require an embedded microprocessor. All of these families are designed for performance-driven applications.

QuickLogic's FPGA Solution

        QuickLogic's FPGAs offer higher performance at lower overall systems cost than competing FPGA solutions, in addition to offering the advantages typically associated with FPGAs. Specifically, our products provide greater design flexibility than standard FPGAs and enable designers of complex systems to achieve rapid time-to-market with highly differentiated products. Our products are based on our ViaLink technology and user-programmable platform, and our associated QuickWorks and QuickTools design software.

        During 2000, we introduced a new FPGA family called Eclipse—devices that offer a host of new system-level features that are ideal for the telecommunications, networking, computer and test applications that require a combination of high-performance, high density and embedded random access memory, or RAM. In addition, we continue to sell our three families of pASIC FPGAs.

The QuickLogic Strategy

        Our objective is to be the indispensable provider of high-speed, flexible, cost-effective ESPs. We feel we can achieve this objective by offering systems manufacturers the ability to accelerate design cycles to satisfy demanding time-to-market requirements. To achieve our objective, we have adopted the following strategies:

Extend Technology Leadership

        Our ViaLink technology, user-programmable platform and proprietary software design tools enable us to offer flexible, high-performance ESP products. We intend to continue to invest in the development of these technologies and to utilize such developments in future innovations of our ESP products. We also intend to focus our resources on building critical systems-level expertise to introduce new ESP products and enhance existing ESP product families. We target applications that are:

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high performance and high complexity;



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broadly used and growing quickly; and



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difficult or impossible to implement in traditional FPGAs.

        Specifically, we will continue to focus our design and marketing efforts on systems manufacturers who sell complex systems within our target applications. These include:

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data communications and telecommunications;



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video/audio and graphics and imaging;



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instrumentation and test;



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high-performance computing; and



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military.

Provide Complete System Solutions

        Our focus on a more targeted set of applications areas will allow us to provide a complete solution to systems manufacturers. This includes not only the device and software, but software drivers,

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reference designs, test boards and complementary intellectual property, or IP, functions. We focus ESP development efforts on three strategic applications areas:

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embedded high performance digital signal processing, or DSP;



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embedded high-performance interconnect; and



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embedded high-performance processing.

Strategic Alliances

        As a part of our ESP strategy, we have engaged with MIPS Technologies, Finisar, UTMC, Tower Semiconductor, and other companies to expand the range of technology that we embed in our products. In addition, we continue to sell through a network of industry sales representatives and distributors. These alliances will be an essential element of our ESP strategy and strength going forward. By leveraging the expertise of our partners in IP development, wafer fabrication and sales, we can devote our effort to the development of targeted, complete ESP products.

Create Innovative, Industry-Leading Customer Services

        We continue to develop and implement innovative ways to serve and communicate with our customers. For example, our WebASIC service allows customers to use our development software to design a circuit, transmit design information over the Internet and receive a QuickLogic ESP or FPGA device programmed with their design (within one business day in North America and Europe or within two business days in Asia). In addition, our ProChannel web-based system allows our distributors to receive quotations, place orders for our products and view their order status over the Internet. This system complements the Electronic Data Interchange systems that we have used for the past several years with our largest customers.

        We have recently added a new class of products and their associated delivery system called WebESP. These products are ESPs or FPGAs that are configured in our factory and sold over the Internet as application specific standard products. The first WebESP products are semiconductor devices that form bridges between electronic systems using various forms of the UTOPIA communication protocol. Our ViaLink, non-volatile programmable logic devices give us the ability to configure the many variables needed to accommodate many different UTOPIA options and ship the devices to systems manufacturers who use them as ASSPs.

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Customers and Markets

        The following chart provides a representative list by industry of our current customers and the markets in which they do business:

Sales and Technical Support

        We sell our products through a network of sales managers, independent sales representatives and electronics distributors in North America, Europe and Asia. In addition to our corporate headquarters in Sunnyvale, we have regional sales operations in Los Angeles, Dallas, Boston, Raleigh, London, Munich, Shin-Yokohama, Shanghai and Hong Kong. Our direct sales personnel and independent sales representatives are responsible for sales and applications support for a given region of responsibility. Our sales managers and independent sales representatives generally focus on major strategic accounts. Our distributor partnerships generally focus on small and medium-sized customers with the assistance of our independent sales representatives.

        Currently in the United States, our three distributors include Cilicon (an Avnet company), Future Electronics, and Impact Technologies, Inc. A network of distributors throughout Europe and Asia supports our international business. These firms work with our regional sales managers in discovering new opportunities, satisfying customer needs, providing technical support and other value-added services. This activity takes place with new customers as well as existing customers. From time-to-time, we add or delete distributors and sales representatives, as appropriate to meet the needs of our company.

        We provide systems manufacturers with comprehensive technical support, which we believe is critical to remaining competitive in the markets we serve. Our factory-based and distributor applications support organizations provide pre-sales and on-site technical support to customers.

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Competition

        The semiconductor industry is intensely competitive and is characterized by constant technological change, rapid rates of product obsolescence and price erosion. Our existing competitors include suppliers of conventional standard products, such as PLX Technology and Applied Micro Circuits Corporation; suppliers of complex programmable logic devices, or CPLDs, including Lattice Semiconductor and Altera; and suppliers of FPGAs, particularly Xilinx and Actel. Xilinx and Altera dominate the PLD market, which together control over 60% of the market, according to inSearch Research, a semiconductor market research firm. Xilinx dominates the FPGA segment of the market while Altera dominates the CPLD segment of the market. We also face competition from companies that offer standard gate arrays, which can be obtained at a lower cost for high volumes and may have gate densities and performance equal or superior to our products. As we introduce additional ESPs, we will also face competition from standard product manufacturers who are already servicing or who may decide to enter the markets addressed by these new ESP devices. In addition, we expect significant competition in the future from major domestic and international semiconductor suppliers. We also may face competition from suppliers of products based on new or emerging technologies.

        We believe that important competitive factors in our market are length of development cycle, price, performance, installed base of development systems, adaptability of products to specific applications, ease of use and functionality of development system software, reliability, technical service and support, wafer fabrication capacity and sources of raw materials, and protection of products by effective utilization of intellectual property laws.

Research and Development

        Our future success will depend to a large extent on our ability to rapidly develop and introduce new products and enhancements to our existing products that meet emerging industry standards and satisfy changing customer requirements. We have made and expect to continue to make substantial investments in research and development and to participate in the development of new and existing industry standards.

        As of February 18, 2002, the research and development staff consisted of 60 employees working in several groups. Our research and development efforts are directed at the complete range of requirements of our ESP products.

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Our process engineering group develops our proprietary ViaLink wafer manufacturing process, oversees product manufacturing and process development with our third-party foundries, and is involved in ongoing process improvements to increase yields and optimize device characteristics.



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Our analog engineering group develops high-performance analog circuits to support our ESP products.



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Our FPGA design engineering group develops high-performance programmable systems that can be used stand-alone or combined with high value dedicated functions to form ESP products.



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Our ASIC design engineering group develops or integrates dedicated IP that is combined with a programmable system to produce ESP products.



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Our FPGA software group develops the design libraries, interface routines and place and route software that allows our customers to use third-party design environments to develop designs for our programmable systems and subsystems.



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Our embedded systems group develops the software required to program and use our MIPS based products.

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        Our research and development expenses for 1999, 2000 and 2001 were $7.4 million, $9.3 million and $14.3 million, respectively. We anticipate that we will continue to commit substantial resources to research and development in the future.

Manufacturing

        We have established close relationships with third-party manufacturers for our wafer fabrication, package assembly, test and programming requirements in an effort to ensure stability in the supply of our products and minimize the risk of localized capacity constraints.

        We currently outsource all of our wafer manufacturing to Cypress Semiconductor Corporation (Cypress) at its Round Rock, Texas facility and to Taiwan Semiconductor Manufacturing Company (TSMC) at its Taiwan facilities. Cypress manufactures our pASIC1 and pASIC2 product families using a three-layer metal, 0.65 micron CMOS process on six-inch wafers. TSMC manufactures our pASIC3, QuickRAM and QuickPCI product families using a four-layer metal, 0.35 micron CMOS process. TSMC also manufactures our Eclipse and other ESP products using a five-layer metal, 0.25 micron process on eight-inch wafers. Our Cypress agreement provides a guaranteed capacity availability. We purchase products from TSMC on a purchase order basis.

        On December 12, 2000 we entered into a Share Purchase Agreement with Tower Semiconductor Ltd. (Tower) under which we agreed to make a $25 million strategic investment in Tower as part of Tower's plan to build a new wafer fabrication facility. The new fabrication facility will produce 200-mm wafers in geometries of 0.18 micron and below, using advanced CMOS technology from Toshiba. In return for our investment, we will receive equity and committed production capacity in the advanced fabrication facility that Tower is building. Tower will develop manufacturing capability for our proprietary ViaLink technology, and supply us with a guaranteed portion of the new fabrication facility's available wafer capacity at competitive pricing, with first production expected in 2002.

        We outsource our product packaging, test and programming to Amkor Technology and ChipPAC, Inc. at their South Korea facilities and to Advanced Semiconductor Engineering at its Taiwan facility, among others.

Employees

        As of February 18, 2002, we had a total of 189 employees worldwide, with 40 people in operations, 60 people in research and development, 22 people in sales, 32 people in marketing and 35 people in administration. We believe that our future success will depend in part on our continued ability to attract, hire and retain qualified personnel. None of our employees is represented by a labor union, and we believe our employee relations are good.

Intellectual Property

        Our future success and competitive position depend upon our ability to obtain and maintain the proprietary technology used in our principal products. We hold 81 U.S. patents and have 12 pending applications for additional U.S. patents containing claims covering various aspects of programmable integrated circuits, programmable interconnect structures and programmable metal devices. In addition, we have two patent applications pending in Japan and one granted. Our issued patents expire between 2009 and 2019. We have also registered six of our trademarks in the U.S. with applications to register an additional two trademarks now pending.

        Because it is critical to our success that we are able to prevent competitors from copying our innovations, we intend to continue to seek patent protection for our products. The process of seeking patent protection can be long and expensive, and we cannot be certain that any currently pending or future applications will actually result in issued patents, or that, even if patents are issued, they will be

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of sufficient scope or strength to provide meaningful protection or any commercial advantage to us. Furthermore, others may develop technologies that are similar or superior to our technology or design around the patents we own.

        We also rely on trade secret protection for our technology, in part through confidentiality agreements with our employees, consultants and third parties. However, employees may breach these agreements, and we may not have adequate remedies for any breach. In any case, others may come to know about or determine our trade secrets through a variety of methods. In addition, the laws of certain territories in which we develop, manufacture or sell our products may not protect our intellectual property rights to the same extent as do the laws of the United States.

        From time to time, we receive letters alleging patent infringement or inviting us to take a license to other parties' patents. We evaluate these letters on a case-by-case basis. In September 1999, we received an offer to license a patent related to field programmable gate array architecture. We have not yet determined whether this license would be necessary or useful and obtainable at a reasonable price. Offers such as these may lead to litigation if we reject the opportunity to obtain the license.

Executive Officers and Directors

        The following table sets forth certain information concerning our current executive officers and directors as of February 18, 2002:

        E. Thomas Hart has served as our President, Chief Executive Officer and a member of our board of directors since June 1994, and as our Chairman since April, 2001. Prior to joining QuickLogic, Mr. Hart was Vice President and General Manager of the Advanced Networks Division at National Semiconductor, a semiconductor manufacturing company, where he worked from September 1992 to June 1994. Prior to joining National Semiconductor, Mr. Hart was a private consultant from February 1986 to September 1992 with Hart Weston International, a technology based management consulting firm. Mr. Hart serves on the board of Insilicon, a provider of electronic design intellectual property. Mr. Hart holds a B.S.E.E. from the University of Washington.

        Michael A. Alford, a co-founder of V3 Semiconductor Inc., joined us in August 2001, serving as Vice President, Application-Specific Standard Products. From April, 1994 to August 2001, Mr. Alford was employed by V3 Semiconductor, a semiconductor manufacturing company, most recently as Chief

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Technical Officer. To facilitate the asset sale and the subsequent windup of V3 as a distinct entity, V3 filed for relief under Chapter 11 of the bankruptcy laws in May 2001. From 1992 to 1994, Mr. Alford was employed by ATI, a manufacturer of multimedia and graphics components for personal computers. Mr. Alford holds a B.E.Sc. (Electrical) degree from the University of Western Ontario.

        John M. Birkner, a co-founder of QuickLogic, has served with us since April 1988, serving as Vice President, Chief Technical Officer since 1993. From September 1975 to June 1986, Mr. Birkner was a fellow at Monolithic Memories, a semiconductor manufacturing company. Mr. Birkner holds a B.S.E.E. from the University of California, Berkeley and an M.S.E.E. from the University of Akron.

        Andrew K. Chan, a co-founder of QuickLogic, has served with us since April 1988, most recently as Vice President, Research and Development. Prior to joining QuickLogic, Mr. Chan was a design engineering manager at Monolithic Memories. Mr. Chan holds a B.S.E.E. in Electrical Engineering from Washington State University and an M.S.E.C. in Electrical Sciences from the University of New York, Stonybrook.

        Hua-Thye Chua, a co-founder of QuickLogic, has served as a member of our board of directors since QuickLogic's inception in April 1988. Since December 1996, Mr. Chua has served as our Vice President, Process Technology. He served as our Vice President of Technology Development from April 1989 to December 1996. During the prior 25 years, Mr. Chua worked at semiconductor manufacturing companies, including Fairchild Semiconductor, Intel and Monolithic Memories. Mr. Chua holds a B.S.E.E. from Ohio University and an M.S.E.E. from the University of California, Berkeley.

        Peter G. Feist served as our Vice President, Worldwide Marketing from June, 2000 until February 15, 2002. From January 1997 to April 2000, Mr. Feist was with GateField, a semiconductor manufacturing company, where he was most recently Senior Vice President, Marketing. From January 1995 to September 1996, he served as Regional Manager, Europe for Hyundai Corporation, Digital Media Division. From April 1985 to December 1994, he worked for LSI Logic, a semiconductor manufacturing company, most recently as Director Strategic Marketing. He holds a Diplom Ingenieur (M.S.E.E.-equivalent) from the University of Dortmund.

        Timothy Saxe joined QuickLogic in May 2001 as our Vice President, Software Engineering. From November 2000 to February 2001, Mr. Saxe was Vice President of FLASH Engineering at Actel, a semiconductor manufacturing company. Mr. Saxe joined Zycad, a design verification tools and services company, in June 1983 and was a founder of Zycad's Gatefield division, a semiconductor manufacturing division, in 1993. Zycad was renamed Gatefield in October 1997. Mr. Saxe became Gatefield's CEO in February 1999 and served in that capacity until Gatefield was acquired by Actel in November 2000. He holds a BSEE degree from North Carolina State University, and an MSEE and a PhD in Electrical Engineering from Stanford University.

        Jeffrey D. Sexton joined QuickLogic in August 2001. Between January 1995 and August 2001, he held several positions at National Semiconductor including Director of Distribution, Regional Sales Manager, Cisco Systems Global Account Manager and OEM Sales Engineer. He holds a BSEE degree from Wright State University in Dayton, OH.

        Reynold W. Simpson has served with us since August 1997, most recently as Senior Vice President and Chief Operating Officer. From February 1996 to July 1997, Mr. Simpson was Vice President of Manufacturing at GateField, a semiconductor manufacturing company. Prior to joining Gatefield, Mr. Simpson was Operations Manager at LSI Logic, a semiconductor manufacturing company, from March 1990 to February 1996 and Quality Director from February 1989 to March 1990. Mr. Simpson holds a Mechanical Engineering Certificate from the Coatbridge Polytechnic Institute in Scotland, a degree in Technical Horology (Mechanical Engineering) from the Barmulloch Polytechnic Institute in

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Scotland and studied for a degree in Electronic Engineering at the Kingsway Polytechnic Institute in Scotland.

        Arthur O. Whipple has served as our Vice President, Finance, Chief Financial Officer and Secretary since April 1998. From April 1994 to April 1998, Mr. Whipple was employed by ILC Technology, a manufacturer of high performance lighting products, as its Vice President of Engineering and by its subsidiary, Precision Lamp, a manufacturer of high-performance lighting products, as its Vice President of Finance and Operations. From February 1990 to April 1994, Mr. Whipple served as the President of Aqua Design, a privately-held provider of water treatment services and equipment. Mr. Whipple holds a B.S.E.E. from the University of Washington and an M.B.A. from Santa Clara University.

        Ronald D. Zimmerman has served as our Vice President, Administration since October 1996. From August 1988 to October 1996, Mr. Zimmerman was Human Resources Director of the Analog Products Group at National Semiconductor, as well as group human resources director of the corporate technology and quality/reliability organizations and the human resources director of corporate administration. Mr. Zimmerman holds a B.A. in Sociology and Psychology and an M.A. in Psychology from San Jose State University.

        Donald P. Beadle has served as a member of our board of directors since July 1997. Since June 1994, Mr. Beadle has been President of Beadle Associates, a consulting firm. From May 1997 to July 1997, Mr. Beadle was a consultant at Interwave Communications, a developer of microcell systems, where he served as Acting Vice President of Sales and Sales Operations. From October 1994 to December 1996, he was a consultant for Asian business development at National Semiconductor. At National Semiconductor, he was Managing Director, Southeast Asia from 1993 until June 1994, Vice President of Worldwide Marketing and Sales, International Business Group from 1987 until 1993, and Managing Director, Europe from 1982 to 1986. Mr. Beadle was employed by National Semiconductor in executive sales and marketing positions for 34 years until June 1994, at which time he was Executive Vice President, Worldwide Sales and Marketing. Mr. Beadle serves on the board of directors of one public company, Komag, a thin film media manufacturer. He received his technical education at the University of Connecticut and the Bridgeport Institute of Engineering.

        Robert J. Boehlke has served as a member of our board of directors since December 2000. Mr. Boehlke was most recently Executive Vice President and Chief Financial Officer of KLA-Tencor, a position he held until his retirement in June 2000. He joined KLA Instruments in 1983 and served as the general manager of various operating groups through 1990 when he became Chief Financial Officer. He was a partner at the investment banking firm of Kidder, Peabody & Company from 1971 until 1983. Mr. Boehlke serves on the boards of LTX, a test equipment manufacturer, Entegris, a manufacturer of materials management products for the semiconductor industry, MEMC Electronic Materials, Inc. and DuPont Photomasks, Inc., manufacturers of materials for the semiconductor industry. He holds a bachelor's degree in engineering from the U.S. Military Academy at West Point and an M.B.A. from Harvard University.

        Michael J. Callahan has served as a member of our board of directors since July 1997. From March 1990 through his retirement in September 2000, Mr. Callahan served as Chairman of the Board, President and Chief Executive Officer of Waferscale Integration, a producer of peripheral integrated circuits. From 1987 to March 1990, Mr. Callahan was President of Monolithic Memories, now a subsidiary of Advanced Micro Devices, a semiconductor manufacturing company. He was Senior Vice President of Programmable Products at Advanced Micro Devices. From 1978 to 1987, Mr. Callahan held a number of positions at Monolithic Memories including Vice President of Operations and Chief Operating Officer. Prior to joining Monolithic Memories, he worked at Motorola Semiconductor, a semiconductor manufacturing company, for 16 years where he was Director of Research and Development as well as Director of Linear Operations. Mr. Callahan serves on the board of Integrated Telecom Express, Inc., which provides asymmetric digital subscriber line chipsets, network protocol

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software, and development tools. Mr. Callahan holds a B.S.E.E. from the Massachusetts Institute of Technology.

Executive Officers

        Our executive officers are elected by, and serve at the discretion of, our board of directors. There are no family relationships among our directors and officers.

Board of Directors

        We currently have authorized five directors. Our directors consist of Messrs. Beadle, Boehlke, Callahan, Chua and Hart. All directors hold office for a term of three years. Our certificate of incorporation provides that our board of directors will be divided into three classes, each with staggered three-year terms. As a result, only one class of directors will be elected at each annual meeting of our stockholders, with the other classes continuing for the remainder of their respective three-year terms. Messrs. Beadle and Callahan have been designated as Class I directors, whose terms expire at the 2003 annual meeting of stockholders; Mr. Chua has been designated as a Class II director, whose term expires at the 2004 annual meeting of stockholders; and Mr. Hart and Mr. Boehlke have been designated as Class III directors, whose terms expire at the 2002 annual meeting of stockholders.

Board Committees

        Our board of directors has an audit committee and a compensation committee.

        Audit Committee.    The audit committee was formed in June 1995 and currently consists of Messrs. Beadle, Boehlke and Callahan. The audit committee reviews the results and scope of the annual audit and other services provided by our independent accountants, reviews and evaluates our internal control functions and monitors financial transactions between us and our employees, officers and directors.

        Compensation Committee.    The compensation committee was formed in June 1995 and currently consists of Messrs. Beadle, Boehlke and Callahan. The compensation committee administers the 1989 stock option plan, 1999 stock plan and 1999 employee stock purchase plan, and reviews the compensation and benefits for our executive officers.

Compensation Committee Interlocks and Insider Participation

        Prior to establishing the compensation committee, the board of directors as a whole performed the functions delegated to the compensation committee. No member of the compensation committee or executive officer of QuickLogic has a relationship that would constitute an interlocking relationship with executive officers or directors of another entity.

ITEM 2. PROPERTIES

        Our principal administrative, sales, marketing, research and development and final testing facility is located in a building of approximately 42,000 square feet in Sunnyvale, California. This facility is leased through 2003 with an option to renew through 2006. The acquisition of V3 during 2001 added approximately 11,000 square feet of engineering and development space in Toronto, Canada. The Toronto facility is leased through January 2005. In addition, during 2001 we leased approximately 4,000 square feet of engineering development space in La Palma, CA near Los Angeles. The La Palma facility is leased through January 2004. We lease, or rent, sales offices in Richardson, TX (leased through March 2003), London (leased through September 2004), Hong Kong (leased through September 2002), Shanghai (rent in six month increments) and Shin-Yokohama. In June 2001 we closed

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our 1,500 square foot engineering office in Hillsborough, Oregon. In December 2001 QuickLogic leased a 4,500 square foot engineering facility in Bangalore, India for the purpose of software development. The Bangalore facility is leased through November 2004. We believe that our existing facilities are adequate for our current needs.

ITEM 3. LEGAL PROCEEDINGS

        On March 29, 2000, Unisys Corporation ("Unisys") brought suit in the United States District Court for the Northern District of California, San Jose Division ("Court"), against QuickLogic seeking monetary damages and injunctive relief. The summons and complaint were served on QuickLogic on April 10, 2000. The Court conditionally dismissed the case with prejudice on October 11, 2001, which dismissal became final thirty days later. We entered into a definitive written settlement agreement on November 8, 2001. The settlement was immaterial to QuickLogic's business, financial condition and operating results.

        On October 26, 2001, a putative securities class action was filed in the U.S. District Court for the Southern District of New York against some investment banks that underwrote QuickLogic's initial public offerings, QuickLogic, and some of QuickLogic's officers and directors. This lawsuit is captioned Turoff v. QuickLogic et al., Case No. 01-CV-9503. Various plaintiffs have filed similar actions asserting virtually identical allegations against over 300 other public companies, their underwriters, and their officers and directors arising out of each company's public offering. The complaint in this case generally alleges that the underwriters obtained excessive and undisclosed commissions in connection with the allocation of shares of Common Stock in the Company's initial public offering and maintained artificially high prices through "tie-in" arrangements which required customers to buy shares in the aftermarket at pre-determined prices. The complaint alleges that QuickLogic and its current officers and directors violated sections of the Securities Act of 1933, and the Securities Exchange Act of 1934 because our registration statements did not disclose the purported misconduct of the underwriters. Plaintiffs seek an unspecified amount of damages on behalf of persons who purchased our stock pursuant to the registration statements. We believe that these allegations are without merit and intend to defend the case vigorously.

ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS

        No matters were submitted to a vote of security holders during the fourth quarter of the fiscal year covered by this report.

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PART II

ITEM 5.  MARKET FOR THE REGISTRANT'S COMMON EQUITY AND RELATED STOCKHOLDER MATTERS

        Our Common Stock has been traded on The Nasdaq Stock Market's National Market under the symbol "QUIK" since October 15, 1999, the date of our initial public offering. The following table sets forth for the periods indicated the high and low closing prices for the Common Stock, as reported on The Nasdaq Stock Market's National Market:

        The last reported sale price of our Common Stock on The Nasdaq Stock Market's National Market was $4.24 per share on February 27, 2002. As of February 27, 2002, there were 23,185,808 shares of Common Stock outstanding that were held of record by approximately 303 stockholders.

        We commenced our initial public offering on October 15, 1999 pursuant to a Registration Statement on Form S-1 (File No. 333-28833) which was declared effective by the Securities and Exchange Commission on October 14, 1999. The Company sold an aggregate of 3,770,635 shares of Common Stock in our initial public offering at an initial price to the public of $10.00 per share. In addition, a selling stockholder sold 3,896,415 shares of Common Stock in our initial public offering at an initial price to the public of $10.00 per share. Our initial public offering has terminated and all shares have been sold. The managing underwriters of our initial public offering were Robertson Stephens, Bear, Stearns & Co. Inc. and SoundView Technology Group. Aggregate proceeds from our initial public offering were $76.7 million, which includes $10.0 million in aggregate proceeds due to the exercise of the underwriters' option to purchase shares to cover over-allotments.

        We paid underwriters' discounts and commissions of $2.6 million and no additional offering expenses in connection with our initial public offering. The total expenses we paid in our initial public offering were $1.2 million, and the net proceeds to us of our initial public offering were $33.9 million.

        The Company completed a follow-on public offering of its common stock on April 12, 2000. The underwriters' over-allotment option was exercised and QuickLogic sold a total of 1,629,269 common shares at $23.50 per share. Proceeds, net of underwriting discounts and commissions and related offering expenses, of $35.5 million were received.

        From October 14, 1999, the effective date of the Registration Statement, to December 31, 2001, the ending date of the reporting period, the approximate amount of net offering proceeds used were $40 million for general business operations. See "Management's Discussion and Analysis of Financial Condition and Results of Operations."

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Dividend Policy

        We have never declared or paid any dividends on our capital stock. We currently expect to retain future earnings, if any, for use in the operation and expansion of our business and do not anticipate paying any cash dividends in the foreseeable future.

Recent Sales of Unregistered Securities

        On August 1, 2001, we acquired capital assets, prepaid expenses, inventory and other assets from V3 Semiconductor, Inc., a Toronto based manufacturer of application specific standard products, in exchange for 2.52 million shares of our common stock with a value of approximately $13.1 million. The shares were issued to V3 pursuant to an exemption under Section 4(2) of the Securities Act of 1933, as amended.

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ITEM 6. SELECTED FINANCIAL DATA

(1)

Contract termination and legal expenses include a charge of $23.0 million in the year ended December 31, 1997 for termination of an agreement with Cypress, and charges of $5.3 million in the year ended December 31, 1997, for legal and settlement costs associated with a cross licensing agreement with Actel Corporation.

(2)

Write down of marketable securities includes a charge of $6.8 million for the write down of equity in Tower. See note 8 of notes to consolidated financial statements.

(3)

Long term obligations at December 31, 1997 include obligations under an Actel cross licensing agreement. At December 31, 1998, this obligation is classified as a current liability. We paid all of our remaining obligations under the agreement on November 3, 1999.

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ITEM 7.  MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS OF OPERATIONS

EXPLANATORY NOTE

        Statements in this section, and elsewhere in this Annual Report on Form 10-K, which express that QuickLogic "believes", "anticipates" or "plans to...", as well as other statements which are not historical fact, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Actual events or results may differ materially as a result of the risks and uncertainties described herein and elsewhere including, in particular, those factors described under "Factors Affecting Future Results."

Overview

        We design and sell field programmable gate arrays, embedded standard products, associated software and programming hardware. From our inception in April 1988 through the third quarter of 1991, we were primarily engaged in product development. In 1991, we introduced our first line of field programmable gate array products, or FPGAs, based upon our ViaLink technology. FPGAs have accounted for substantially all of our product revenue to date. We currently have four FPGA product families: pASIC 1, introduced in 1991; pASIC 2, introduced in 1996; and pASIC 3, introduced in 1997. We introduced our Eclipse family of FPGAs in 2000. The newer product families generally contain greater logic capacity, but do not necessarily replace sales of older generation products.

        In September 1998, we introduced QuickRAM, our first line of embedded standard products, or ESPs. Our ESPs are based on our FPGA technology. In April 1999, we introduced QuickPCI, our second line of ESPs. Revenue for our QuickRAM and QuickPCI products together accounted for approximately 22% of our total revenue in 2001. During 2000, we introduced the QuickFC, QuickDSP, QuickSD and QuickMIPS families of ESPs, which accounted for about 1% of total revenue in 2001. We also license our QuickWorks and QuickTools design software and sell our programming hardware, which together have typically accounted for less than 2% of total revenue.

        In April 2001, we signed a definitive agreement with V3 Semiconductor, Inc. to acquire certain assets of V3 in a stock transaction. We also entered into a manufacturing and distribution agreement with V3 pending the sale in order to ensure continued distribution of V3's products to its customers. V3, based in Toronto, Ontario, manufactured application specific standard products, or ASSPs, that enhance high-speed data throughput within telecommunications and Internet infrastructure systems.

        To facilitate the asset sale and the subsequent windup of V3 as a distinct entity, V3 filed for relief under Chapter 11 of the bankruptcy laws in May 2001. In August 2001, we completed the acquisition of certain assets of V3, for approximately 2.5 million shares of our common stock, valued at $13.1 million. The acquisition is designed to accelerate our ESP strategy by strengthening our ability to develop and market system-level products for the communications and networking markets. Upon completion of V3's bankruptcy proceedings, V3 is expected to distribute these shares to its creditors and stockholders. The distributed shares will then be freely tradeable on the open market. The acquisition was accounted for as a purchase.

        On December 12, 2000, we entered into a Share Purchase Agreement (the "Agreement") with Tower Semiconductor Ltd. ("Tower"). Under the Agreement, we agreed to make a $25 million strategic investment in Tower as part of Tower's plan to build a new wafer fabrication facility. The new fabrication facility will produce 200-mm wafers in geometries of 0.18 micron and below, using advanced CMOS technology from Toshiba. In return for the investment, we will receive equity and committed production capacity in the advanced fabrication facility that Tower is building. In connection with the Agreement, we also entered into a foundry agreement under which we are entitled to a certain amount of wafer purchase credits. Up to 15% of order value can be applied against these credits in future wafer purchases from Tower. The amount of credits is determined upon each share purchase

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transaction and is calculated based on the difference between our share purchase exercise price and the higher of $12.50 and Tower's average stock price for 30 days preceding a purchase transaction. Under the terms of the Agreement, our investment will be made in several stages over an approximately 22-month period, against satisfactory completion of key milestones for the construction, equipping and commencement of production at the new wafer fabrication facility.

        Pursuant to the Agreement, we purchased 533,310 ordinary shares of Tower and future wafer purchase credits for an aggregate purchase price of $14.0 million in fiscal 2001. We agreed to purchase an additional 366,690 ordinary shares of Tower in three equal increments upon occurrence of certain events relating to the construction of the fabrication facility. We agreed to purchase two thirds of these additional shares in fiscal 2002, and the remainder in 2003. The ordinary shares are restricted, and we account for the shares under the cost method, based on the fact that we do not have significant influence over Tower's operations.

        During the third quarter of fiscal 2001, due to an "other-than-temporary" decline in the value of the stock, we wrote down our investment in Tower, recording a pre-tax, non-operating loss of $6.8 million. Also, in October 2001, approximately $5.3 million of our wafer purchase credits were converted to 418,616 ordinary shares in Tower. At December 31, 2001, the wafer credits from Tower totalled $1.8 million and are included in other assets on the balance sheet. At December 31, 2001, we owned a total of 951,926 shares in Tower, with a book value of $5.4 million.

        We sell our products through two channels. We sell the majority of our products through distributors who have contractual rights to earn a negotiated margin on the sale of our products. We refer to these distributors as point-of-sale distributors. We defer recognition of revenue for sales of unprogrammed products to these point-of-sale distributors until after they have sold these products to systems manufacturers. We recognize revenue on programmed products at the time of shipment. Approximately 65% of our products sold by point-of-sale distributors are programmed by us and are not returnable by these point-of-sale distributors. We also sell our products directly to systems manufacturers and recognize revenue at the time of shipment. The percentage of sales derived through each of these channels in 1999 was 80% and 20% respectively. In 2000 it was 69% and 31%, respectively, and 74% and 26% in 2001, respectively.

        Four distributors accounted for 24%, 11%, 10%, and 6% of sales, respectively, in 1999. Five distributors accounted for 20%, 8%, 7%, 6% and 6% of sales, respectively, in 2000 and five distributors accounted for approximately 33%, 15%, 8%, 8% and 7% of sales, respectively, in 2001. We expect that a limited number of distributors will continue to account for a significant portion of our total sales. We believe the company's products are proprietary and sole source, and that the loss of a particular distributor would not result in a short term disruption in sales of our products, since our customers would either buy our products from another distributor or directly from us.

        Our international sales were 48%, 38% and 35% of our total sales for 1999, 2000 and 2001, respectively. We expect that revenue derived from sales to international customers will continue to represent a significant and growing portion of our total revenue. All of our sales are denominated in U.S. dollars.

        Average selling prices for our products typically decline rapidly during the first six to 12 months after their introduction, then decline less rapidly as the products mature. We attempt to maintain gross margins even as average selling prices decline through the introduction of new products with higher margins and through manufacturing efficiencies and cost reductions. However, the markets in which we operate are highly competitive, and there can be no assurance that we will be able to successfully maintain gross margins. Any significant decline in our gross margins will materially harm our business.

        We outsource the wafer manufacturing, assembly and test of all of our products. We rely upon Taiwan Semiconductor Manufacturing Company and Cypress Semiconductor Corporation to

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manufacture our products, and we rely primarily upon Amkor Technology and ChipPAC, Inc. to assemble and test our products. Under our arrangements with Cypress, we are obligated to provide forecasts and enter into binding obligations for anticipated purchases. This limits our ability to react to fluctuations in demand for our products, which could lead to excesses or shortages of wafers for a particular product.

Results of Operations

        The following table sets forth the percentage of revenue for certain items in our statements of operations for the periods indicated: