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FORM 10-K

Commission File Number: 0-16617

ALTERA CORPORATION

(408) 544-7000

Securities registered pursuant to Section 12(b) of the Act:

Securities registered pursuant to Section 12(g) of the Act:

Indicate by check mark whether the registrant: (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes x No o

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. o

Indicate by check mark whether the registrant is an accelerated filer (as defined in Exchange Act Rule 12b-2). Yes x No o

The aggregate market value of the registrant’s common stock held by non-affiliates of the registrant was approximately $3,790,000,000 as of June 28, 2002, based upon the closing sale price on the Nasdaq National Market for that date. For purposes of this disclosure, shares of common stock held by persons who hold more than 5% of the outstanding shares of common stock and shares held by executive officers and directors of the registrant have been excluded because such persons may be deemed affiliates. This determination is not necessarily conclusive.

There were 382,148,741 shares of the registrant’s common stock issued and outstanding as of February 18, 2003.

DOCUMENTS INCORPORATED BY REFERENCE

Item 6 of Part II incorporates information by reference from the Annual Report to Stockholders for the fiscal year ended December 31, 2002.

Items 10, 11, 12, and 13 of Part III incorporate information by reference from the Proxy Statement for the Annual Meeting of Stockholders to be held on May 6, 2003.

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FORWARD-LOOKING STATEMENTS

This report contains forward-looking statements, which are provided under the “safe harbor” protection of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally written in the future tense and/or are preceded by words such as “will,” “may,” “should,” “could,” “expect,” “suggest,” “believe,” “anticipate,” “intend,” “plan,” or other similar words. Forward-looking statements include statements regarding (1) our gross margins and factors that affect gross margins, such as the costs of raw materials, our ability to absorb manufacturing costs, trends in selling prices, and the sale of previously reserved inventory; (2) our research and development efforts; (3) the commercial success of our new products; (4) trends in future sales; (5) the availability of cash to finance operations; (6) our ability to hold our fixed income investments until maturity; and (7) future economic conditions.

Forward-looking statements are not guarantees of future performance and involve risks and uncertainties. The forward-looking statements contained in this report are based on information that is currently available to us and expectations and assumptions that we deem reasonable at the time the statements were made. We do not undertake any obligation to update any forward-looking statements in this report or in any of our other communications, except as required by law. All such forward-looking statements should be read as of the time the statements were made and with the recognition that these forward-looking statements may not be complete or accurate at a later date.

Many factors may cause actual results to differ materially from those expressed or implied by the forward-looking statements contained in this report. These factors include, but are not limited to, those risks set forth under “Management’s Discussion and Analysis of Financial Condition and Results of Operations—Risk Factors.”

PART I

Item 1. Business.

Founded in 1983 and reincorporated in Delaware in 1997, Altera Corporation designs, manufactures, and markets (1) high-performance, high-density programmable logic devices, or PLDs; (2) pre-defined design building blocks known as intellectual property, or IP, cores; and (3) associated development tools. Our PLDs, which consist of field-programmable gate arrays, or FPGAs, and complex programmable logic devices, or CPLDs, are semiconductor integrated circuits that are manufactured as standard chips that our customers program to perform desired logic functions within their electronic systems. Our customers can license IP cores from us for implementation of standard functions in their PLD designs. Customers develop, compile, verify, and program their PLD designs using our proprietary development software, which operates on personal computers and engineering workstations.

We were one of the first suppliers of complementary metal oxide semiconductor, or CMOS, PLDs and are currently a global leader in this market. Today, we offer a broad range of PLDs that offer unique features as well as differing densities and performance specifications. Our products serve a wide range of markets, including telecommunications, data communications, computing and storage, consumer, and industrial applications. Some of our major products are more fully described below.

Our headquarters facility is located at 101 Innovation Drive, San Jose, California 95134, and our website is www.altera.com. Our common stock trades on the Nasdaq National Market under the symbol “ALTR.”

Integrated Circuit and ASIC Overview

Three principal types of digital integrated circuits are used in most electronic systems: (1) processors, (2) memory, and (3) logic.

	•	Processors, which include microprocessors, microcontrollers, and digital signal processors, or DSPs, are typically used for control and central computing tasks;
	•	Memory is used to store programming instructions and data; and
	•	Logic is typically used to manage the interchange and manipulation of digital signals within a system.

While system designers employ a relatively small number of standard architectures to meet their processor and memory needs, they require a wide variety of logic circuits to differentiate their end products. In addition, competitive pressures force

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The majority of the CMOS logic market is made up of application-specific integrated circuits, or ASICs. The ASIC segment of the CMOS logic market is comprised of (1) programmable logic, (2) gate arrays, and (3) cell-based integrated circuits, also referred to as standard cells. In a broad sense, all of these devices are competitive with each other as they generally may be used in the same types of applications in electronic systems. However, differences in cost, performance, density, flexibility, ease of use, and time to market dictate the extent to which they may be directly competitive for particular applications.

A primary advantage of programmable logic over gate arrays and standard cells is that it allows for shorter design cycles, meeting customers’ needs for quick time to market. In contrast to gate array and standard cell users, PLD users program their design directly into the PLD and can have custom chips that are fully functioning and verified at the time the design is completed. As a result of user programmability, PLD customers may experiment and revise their designs in a relatively short amount of time and with minimum development cost. The time-to-market advantage of PLDs is complemented by the added benefit of field upgradeability, which generally enables PLD users to modify the PLD design after the customer’s electronic system has been shipped.

Due to their programmability, however, PLDs generally have a larger die size and associated higher per-unit cost when compared to standard cells and gate arrays, which are customized during manufacturing at the chip fabrication facility and hence have a fixed function. While the customized manufacturing of standard cells and gate arrays can result in more optimized chip performance and lower per-unit cost than PLDs, it typically requires higher up-front costs and longer manufacturing lead times.

Historically, due to their lower per-unit costs, standard cells and gate arrays have been viewed as more cost effective than PLDs for large-volume, low-cost applications such as consumer electronics. Consequently, the unit volume of a PLD design is typically lower than that for a standard cell or gate array design. Additionally, some customers may choose to prototype with PLDs for initial engineering development and then re-design to a standard cell in volume production for lower per-unit cost. While such re-designs have always been an aspect of the PLD business, we believe that the following factors are driving electronic systems manufacturers to use PLDs for their systems’ entire life cycle: (1) the continual reduction in the price premium of programmable logic; (2) the ever-shortening product life cycle of many electronic systems; and (3) the use of more advanced chip manufacturing technology, which elevates the non-recurring engineering cost and risk of standard cells.

We believe that the adoption of more advanced chip manufacturing technology, which is increasing the total cost of chip development, is reducing the cost advantage of standard cells and gate arrays. The cost and time for us to develop a PLD is comparable to the cost and time for others to develop a gate array or standard cell. Since each of our PLDs is sold to hundreds or thousands of customers, we spread development costs across our wide customer base. In contrast, gate array and standard cell suppliers build fixed, custom chips for a single customer for use in a single application, thus imposing a high up-front cost on the customer. These costs increase as chip manufacturing technology advances and becomes more complex. Consequently, we believe that this factor is driving more applications toward the use of PLDs rather than standard cells and gate arrays despite the higher per-unit cost of PLDs.

Strategy and Competition

We believe that competitive pressures to improve chip functionality, performance, reliability, and cost are driving customers increasingly towards system-on-a-programmable-chip, or SOPC, solutions. We define a SOPC solution to be a high-density PLD containing three or more of the following: (1) logic, (2) memory, (3) high-speed input/output, or I/O, and (4) a processor. With SOPC solutions, system designers require less, if any, separate microprocessor or memory chips, thereby allowing them to reduce the size and cost of their systems. User programmability satisfies the need for custom circuitry and rapid changes, thereby enhancing time to market.

In order to capture a larger percentage of our customer’s bill of materials for semiconductors, we are focused on providing the most advanced SOPC solutions. To accomplish this goal, we strive to offer our customers:

	•	PLDs with the speed, density, functionality, and package types to meet their specific needs;

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	•	HardCopyTM devices that enable our customers to move from a PLD to a low-cost, custom implementation of their designs;
	•	Optimized, pre-verified system-level IP cores to speed their design process;
	•	State-of-the-art development tools that offer low cost and ease of use and compatibility with other industry-standard electronic design automation, or EDA, tools; and
	•	A complete customer support system.

We experience significant direct competition from other companies that are in the programmable logic sub-segment, including Xilinx, Inc. and Lattice Semiconductor Corporation. We expect that as the dollar volume of the programmable logic sub-segment grows, the attractiveness of this sub-segment to larger competitors will continue to increase.

Principal competitive factors in the programmable logic sub-segment include:

	•	The capability of software development tools and IP cores;
	•	Device performance and features;
	•	Quality and reliability;
	•	Pricing and availability;
	•	Technical service and customer support; and
	•	Technical innovation.

We believe that we compete favorably with respect to these factors and that our proprietary device architecture and our installed base of software development systems may provide some competitive advantage. We have been able to introduce new product families that, as compared to their predecessors, provide greater functionality at a lower price for any given density because of unique architectural innovation and advanced technologies.

We also believe that in certain circumstances these new product families compete favorably against ASICs as well as against other types of chips such as microcontrollers, microprocessors, and DSPs. The functionality offered by these other types of chips can be implemented in PLDs using pre-built and pre-verified IP cores. An IP core is typically offered in either a “hard” or “soft” form. A hard IP core is embedded into the silicon of our chips. A soft IP core is a design file that our customers can license for integration into their overall PLD design. By incorporating more functionality and logic capacity on a programmable fabric while providing the necessary design tools and IP cores to design a reliable system, we believe we can build upon the advantages of PLDs over competing solutions.

As is true of the semiconductor industry as a whole, the ASIC segment and the PLD sub-segment are intensely competitive and are characterized by rapid technological change, rapid rates of product obsolescence, and price erosion. All of these factors may influence our future operating results. For a discussion of risk factors associated with our strategy and competition, see Item 7—Risk Factors—“Our financial results depend on our ability to compete successfully in the highly competitive semiconductor industry” and “Our future success depends on our ability to define, develop, and sell new products that achieve market acceptance.”

Products

Our products consist primarily of devices, IP cores, and proprietary development tools. Altogether, these products form a comprehensive solution for the implementation of SOPC applications. A brief overview of these products follows.

Devices

Our devices fall into the following four categories: (1) FPGAs, (2) CPLDs, (3) low-cost, masked devices, and (4) configuration devices, which store the programming code for our FPGAs. These devices span multiple architectures and device families, with a total of more than 1,000 product options. Each device family offers unique functional benefits and differing density and performance specifications for implementing particular applications.

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FPGAs

Our FPGAs consist of general-purpose FPGAs and embedded IP-based FPGAs.

General-Purpose FPGAs

Our general-purpose FPGA products, consisting of our Stratix^TM, Cyclone^TM, APEX^TM II, APEX, FLEX®, and ACEX® product families, are built using the most advanced CMOS static random access memory, or SRAM, process technology and address a broad range of applications in telecommunications, data communications, computing and storage, consumer, and industrial markets. The basic logic building block in a general-purpose FPGA is the logic element. With more logic elements, an FPGA can support more logic circuitry. In addition to the number of logic elements, the amount of embedded RAM within general-purpose FPGAs is also important in user device selection. Our general-purpose FPGAs currently provide up to 79,040 logic elements and up to 7 megabits of RAM in a single device, while offering competitive logic core and I/O performance levels.

Some of our major general-purpose FPGAs are more fully described below:

STRATIX: The Stratix architecture was publicly announced in February 2002 and shipments commenced in May 2002. Based on a 1.5-V, 0.13-micron process, the Stratix device family (1) provides a high-bandwidth architecture that enables block-based design methodology for enhanced time to market, (2) is presently available in densities ranging from 10,570 to 79,040 logic elements, (3) includes up to 7 megabits of embedded RAM, and (4) contains all-layer-copper interconnect technology, which results in greater performance compared to traditional aluminum/ tungsten interconnect. Our Stratix devices are also the first FPGAs to contain embedded DSP capability and various sizes of embedded memory blocks. Embedded DSP blocks provide fast performance for applications such as encryption and filtering in wireless communications, image processing in digital entertainment, and quality of service algorithms in data communications. Stratix devices support a wide array of high-speed, standard interfaces allowing Stratix devices to be suitable for applications including high-bandwidth routers and switches, semiconductor testers, medical imaging, and advanced data storage systems.

CYCLONE: The Cyclone architecture was announced in September 2002 and devices began shipping in December 2002. Cyclone devices are built on a cost-optimized, all-copper 1.5-V, 0.13-micron process, and offer powerful functionality at a low cost. With up to 20,060 logic elements and 288 kilobits of RAM, Cyclone devices can integrate many complex functions. The combination of a low-cost structure with abundant device resources makes Cyclone devices ideal for high-volume applications in areas such as digital set-top boxes, DVD player/ recorder systems, automotive telematics, and plasma displays.

APEX II: Utilizing a second-generation APEX architecture, the APEX II device family is designed to address the increasing performance and bandwidth requirements of a wide range of applications. These devices are built on 1.8-V, 0.13-micron and 0.15-micron processes and include all-layer-copper interconnect technology. They range in density from 16,640 to 67,200 logic elements and include over 1.0 megabit of embedded RAM.

APEX 20K, APEX 20KE, and APEX 20KC: Based on the APEX architecture, the 2.5-V APEX 20K, 1.8-V APEX 20KE, and 1.8-V APEX 20KC device families provide design flexibility and efficiency for high-performance SOPC applications. The APEX 20KC family utilizes copper for all layers of metal interconnect. Devices in these families (1) range in density from 1,200 to 51,840 logic elements, (2) include up to 432 kilobits of embedded RAM, and (3) utilize an embedded system block, or ESB, to embed content addressable memory, or CAM, used in packet switching. Additionally, these devices contain enhanced phase-locked loops, or PLLs, for high-speed clock management, and LVDS.

FLEX 10K, FLEX 10KA, and FLEX 10KE: Based on the FLEX 10K architecture, which was the first PLD architecture to provide on-chip embedded memory, the 5.0-V FLEX 10K, 3.3-V FLEX 10KA, and 2.5-V FLEX 10KE device families offer embedded array blocks, or EABs, to provide a combination of logic and embedded RAM on a single-chip architecture for high-speed, high-bandwidth applications. These families range in density from 576 to 12,160 logic elements and include up to 96 kilobits of embedded RAM.

ACEX 1K: Our ACEX 1K device family, which combines logic elements and EABs, offers complete system-level integration on a single device for cost-sensitive, volume-driven applications such as cable modems, xDSL modems, low-cost switches, and routers. Devices in this family range in density from 576 to 4,992 logic elements, include up to 48 kilobits of embedded RAM, and operate at a 2.5-V supply voltage.

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Embedded IP-Based FPGAs

As a complement to our general-purpose FPGAs, our embedded IP-based FPGAs combine a general-purpose FPGA architecture with embedded IP cores. Together, these two elements comprise a fully integrated and flexible, customizable solution for use in targeted applications. Our embedded IP-based FPGAs consist of our Excalibur^TM devices, which are well-suited for applications requiring high-performance embedded microprocessors, and our Stratix GX and Mercury^TM devices, which are best employed in applications that need embedded transceiver capability for ultra high-speed data transfer.

Our embedded IP-based FPGAs are more fully described below:

EXCALIBUR EMBEDDED PROCESSOR SOLUTIONS: Our Excalibur solutions combine logic, memory, and an embedded processor core, which together allow engineers to integrate an entire system on a single PLD for a wide range of applications, from 3G base stations, embedded routers, microcontrollers, and network processors to industrial control and factory automation. The Excalibur solutions consist of two embedded processor architectures: (1) our Nios® soft core embedded processor solution and (2) the ARM®-based embedded processor solution. The Nios soft core utilizes a reduced instruction set computing, or RISC, architecture and is a cost-competitive and flexible alternative to discrete microcontroller solutions. The Nios soft core can be efficiently implemented in all of our general-purpose FPGA devices as well as in our IP-based FPGA products. The ARM-based embedded processor PLD family uses technology licensed from ARM Limited and consists of multiple devices that each contains an ARM-based RISC processor core. These ARM-based Excalibur devices provide our customers with enhanced integration and royalty-free technology access for applications requiring the capability and complexity of an ARM processor while also needing the flexibility and customization of a general-purpose FPGA.

STRATIX GX: The Stratix GX device family combines 3.125 Gbps per channel transceiver technology with our Stratix FPGA architecture. Announced in November 2002 with initial shipments to customers in January 2003, Stratix GX devices are built on a 1.5-V, 0.13-micron, all-layer-copper SRAM process and contain up to 20 transceiver channels, offering system architects in the broad marketplace—anywhere from communications to high-end consumer electronics to mass storage systems—a low-risk path to 3.125 Gbps transceiver capability. Stratix GX devices are ideal for implementing common interface protocols including proprietary systems that require data rates up to 3.125 Gbps, while providing lower power per channel than competing solutions. Devices in this family range in density from 10,570 to 41,250 logic elements and contain up to 3 megabits of RAM.

MERCURY: Our first IP-based FPGAs aimed at high-speed serial-interface applications, Mercury devices address a wide range of serial backplane, chip-to-chip, and line-side applications. Providing speeds of up to 1.25 Gbps per channel, these devices integrate a high-speed clock data recovery-enabled transceiver with a performance-optimized programmable logic core. Devices in this family range in density from 4,800 to 14,400 logic elements and include up to 112 kilobits of embedded RAM.

CPLDs

Our CPLD products, consisting of our MAX® and Classic^TM product families, are built using CMOS floating-gate process technology and address a wide range of high-speed glue logic functions found in a broad range of electronics equipment in the telecommunications, data communications, computing and storage, consumer, and industrial markets. Glue logic is basic logic that enables the interaction of multiple subsystem components. The basic logic building block in a general-purpose CPLD is the macrocell. Therefore, the total number of macrocells within CPLDs is often used to gauge relative logic density. Another critical metric used in gauging CPLD performance is the total propagation delay, or t_PD, from an input pin to an output pin. Our MAX CPLDs provide over 500 macrocells in a single device with t_PD specifications as fast as 3.5 nanoseconds.

Some of our major CPLDs are more fully described below:

MAX 7000, MAX 7000S, MAX 7000A, and MAX 7000B: The 5.0-V MAX 7000, 5.0-V MAX 7000S, 3.3-V MAX 7000A, and 2.5-V MAX 7000B device families are among the most widely used programmable logic families in the industry. These device families provide high-density, high-speed, I/O-intensive programmable logic solutions for a broad range of glue logic applications, including state machines, control functions, and address decoding. Devices in these families range in density from 32 to 512 macrocells and provide t_PD values as fast as 3.5 nanoseconds.

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MAX 3000A: The 3.3-V MAX 3000A low cost devices, which range in density from 32 to 512 macrocells, target high-volume, low-cost glue logic applications.

Masked Devices

The per-unit price of high-density FPGAs traditionally makes them suitable only as a development and prototyping tool for our customers. Our HardCopy family, described below, offers customers with a conversion path from a high-density FPGA to a non-FPGA production device.

HARDCOPY: For our highest-density FPGA products, our HardCopy devices combine proprietary silicon design and an automated process to offer our customers a seamless migration path to a mask-programmed implementation of their designs for low-cost and high-volume applications. As a result, HardCopy devices extend the flexibility, power, and time-to-market advantages of high-density FPGAs to high-volume, more cost-sensitive applications traditionally covered by standard cells and gate arrays. HardCopy devices offer up to a 70% die size reduction, resulting in a lower cost for customers seeking a high-volume production solution in our highest density FPGAs.

Intellectual Property Cores

IP cores are pre-verified building blocks for implementing standard system-level functions within a PLD design. Soft IP cores available for use in our devices consist of MegaCore® functions, which we license to our customers, and Altera Megafunction Partners Program, or AMPP^SM, cores, which are licensed to our customers by third parties. With IP cores, system designers can focus more time and energy on improving and differentiating the unique aspects of their system design, rather than spending time designing common off-the-shelf functions from the ground up. As a result, IP cores are essential to providing our customers SOPC solutions that enable higher levels of integration and faster time to market. Today, we offer a broad range of soft IP cores for various system blocks for DSP algorithms, bus interfaces, memory controllers, telecommunications, data communications, microprocessors, and peripherals. Prior to licensing a soft IP core, customers may download an encrypted soft IP core from our web site and verify that it works in their own system design. While licensing soft IP cores represents a small portion of our total revenues, we believe our investment in this area enhances our competitive position relative to other ASIC suppliers as well as PLD suppliers.

Development Tools

Our proprietary development tools, consisting primarily of the Quartus® II and MAX+PLUS® II software, enable our customers to successfully complete all necessary PLD design steps. Our tools enhance engineering productivity by facilitating design entry, design compilation, design verification, and device programming during the initial design and subsequent design revisions.

Our development tools can be used on a variety of computer platforms and have built-in interfaces with other engineering design software, thus making it possible for customers to utilize their existing design environment. Our Quartus II and MAX+PLUS II software development tools run under the Microsoft Windows and UNIX (including Solaris, HP-UX, and Linux) operating environments. Our development tools also provide interfaces to many industry-standard EDA tools, including those offered by Mentor Graphics Corporation, Synplicity, Inc., and Synopsys, Inc.

Like soft IP cores, our licensing of development tools represents a small portion of our total revenues, but provides a critical and necessary element of our market strategy, and can drive our success in competing for design wins against other ASIC suppliers as well as PLD suppliers.

Research and Development

Our research and development activities have focused primarily on PLDs and on the associated development software and hardware. We have developed these related products in parallel to provide software support to customers upon device introduction. As a result of our research and development efforts, we have introduced during the past three years a number of new families, such as the Stratix, Stratix GX, Cyclone, APEX II, and HardCopy device families, the Excalibur embedded processor solutions, and the Quartus II development platform. We have also redesigned a number of our products to accommodate new wafer fabrication processes.

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Our research and development expenditures were $182.8 million in 2002, $170.9 million in 2001, and $178.7 million in 2000. Excluding a $6.3 million one-time charge for acquired in-process research and development, our research and development expenditures in 2000 were $172.4 million. We have not capitalized research and development or software costs to date. We intend to continue to spend substantial amounts on research and development in order to continue to develop new products and achieve market acceptance for such products, particularly in light of the industry pattern of short product life cycles and increasing competition within the CMOS logic market.

Patents, Trademarks, and Licenses

We generally rely on intellectual property law, including patent, copyright, trademark, and trade secret laws, to establish and maintain our proprietary rights in products and technology. As of December 31, 2002, we held a total of 587 issued United States patents and 140 patents issued in other countries relating to various aspects of our products and technology; we also have a number of patent applications currently pending. Also, we have used, registered, and applied to register certain trademarks and service marks to distinguish our products, technologies, and services from those of our competitors in the United States and foreign countries. In addition, we file registrations in the United States under the Semiconductor Chip Protection Act to protect our chip designs. Finally, we have entered into technology licensing agreements that give us rights to design, manufacture, and package products using certain intellectual property owned by others. In July 2001, we entered into a settlement agreement with Xilinx under which we settled all pending litigation with Xilinx. As part of the settlement agreement, we entered into a royalty-free patent cross license agreement with Xilinx, including a prohibition of further patent litigation between the two companies through July 2006. In connection with the settlement agreement, we paid Xilinx a one-time payment of $20 million. Similarly, in July 2001 we entered into a settlement agreement with Lattice under which we settled all pending patent litigation with Lattice. As part of the settlement agreement, we entered into a royalty-free patent cross license agreement with Lattice, including a multi-year prohibition of further patent litigation between the two companies. No payments were made by Altera or Lattice as part of the settlement.

When necessary, we seek to enforce our intellectual property rights. Although we believe that protection afforded by our intellectual property rights has value, the rapidly changing technology in the semiconductor industry makes our future success dependent primarily on the innovative skills, technological expertise, and management abilities of our employees rather than on our patent, trademark, or other proprietary rights. For a discussion of risk factors associated with our patents, trademarks, and licenses, see Item 3, Item 7—Risk Factors—“Our intellectual property rights may not provide meaningful protection from our competitors” and “We may face significant costs arising from intellectual property litigation,” and Note 13 to our consolidated financial statements.

Marketing and Sales

We market our products worldwide through a network of distributors and direct sales personnel. In the United States and Canada, we also rely on a network of independent sales representatives. From time to time, we may add or remove independent sales representatives or distributors from our selling organization as we deem appropriate to the level of business.

Throughout the United States, we have domestic sales offices in major metropolitan areas. Our direct sales personnel and independent sales representatives focus on strategic and key accounts. Distributors generally focus selling activities on the broad base of small- and medium-size customers and provide warehousing and logistics services to all of our customers. Our primary distributor in the United States is Arrow Electronics, Inc., which is responsible for creating customer demand from its customer base, providing technical support and other value-added services, filling customers’ orders, and stocking our products.

Our international business is supported by a network of distributors in major European countries, Japan, and various countries throughout Asia Pacific. In addition, we maintain international sales support offices in the metropolitan areas of Bangalore, Beijing, Helsinki, Hong Kong, London, Munich, Ottawa, Paris, Seoul, Shanghai, Stockholm, Stuttgart, Taipei, Tokyo, and Turin.

Through 2002, all international sales were denominated in U.S. dollars. For the year ended December 31, 2002, worldwide sales through distributors for subsequent resale to original equipment manufacturers, or OEMs, or their subcontract manufacturers accounted for over 95% of total sales. In 2002, 2001, and 2000, two distributors accounted for more than 10% of sales. Arrow was, and continues to be, our largest distributor. Arrow on a worldwide basis accounted for 53% of sales in

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For a detailed description of our sales by geographic region, see Item 7 and Note 14 to our consolidated financial statements. For a discussion of the risk factors associated with our foreign operations, see Item 7—Risk Factors—“We depend on international sales for a majority of our total sales” and “Our business is subject to tax risks associated with being a multinational corporation.”

Backlog

Our backlog consists of OEM orders and distributor orders that are each requested for delivery within the next three months. Our backlog of orders on December 31, 2002 was approximately $183.3 million compared to $119.6 million on December 31, 2001. The increase in backlog is attributable to an increase in sales, together with an increase in advance orders made by our distributors and OEMs.

Historically, backlog has been a poor predictor of future customer demand. While our backlog can increase during periods of high demand and supply constraints, our orders are generally cancelable without significant penalty at the option of the purchaser. Further, we defer recognition of revenue on shipments to distributors until the product is resold. For all of these reasons, backlog as of any particular date should not be used as a reliable predictor of sales for any future period.

Customer Support

Customer support and service are important aspects of selling and marketing our products. We provide several levels of technical user support, including applications assistance, design services, and customer training. Also, our applications engineering staff publishes data sheets and application notes, conducts technical seminars, and provides design assistance via the Internet and electronic links to the customer. Finally, as a service to our customers, inventory is maintained by us and our distributors to meet their short-term delivery needs for our products.

Manufacturing

Wafer Supply

We do not directly manufacture our silicon wafers. Instead, our silicon wafers are produced using various semiconductor foundries. This enables us to take advantage of these suppliers’ high-volume economies of scale and also gives us direct and more timely access to advancing process technology. We purchase nearly all of our silicon wafers from Taiwan Semiconductor Manufacturing Company, or TSMC, and the remaining portion from Sharp Corporation. In the past, we have used other foundry vendors, and we may establish additional foundry relationships as such arrangements become economically useful or technically necessary. For a discussion of risk factors associated with our wafer supply arrangements, see Item 7—Risk Factors—“We depend entirely on independent subcontractors to supply us with finished silicon wafers” and “Conditions outside the control of our independent subcontractors may impact their business operations.”

Testing and Assembly

After wafer manufacturing is completed, each wafer is tested using a variety of test and handling equipment. Such wafer testing is accomplished at TSMC, Sharp, and our San Jose pilot line facility, which is used primarily for new product development. This testing is performed on equipment owned by us and consigned to our vendors.

Resulting wafers are then shipped to various assembly suppliers in Asia, where good die are separated into individual chips that are then encapsulated in packages. We employ a number of independent suppliers for assembly purposes. This enables us to take advantage of these subcontractors’ high-volume economies of scale, supply flexibility, and gives us direct and more timely access to advancing packaging technology. We purchase almost all of our assembly services from Amkor Electronics, Inc. in Korea and the Philippines, ASAT Limited in Hong Kong, Advanced Semiconductor Engineering, Inc., or ASE, in Malaysia and Taiwan, and Fujitsu Microelectronics, Inc. in Japan.

Following assembly, each of the packaged units receives final testing, marking, and inspection prior to shipment to customers. We obtain almost all of our final test and back-end operation services from Amkor, ASAT, and ASE. Final

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For a discussion of risk factors associated with our testing and assembly arrangements, see Item 7—Risk Factors—“We depend on independent subcontractors, located primarily in Asia, to assembly and test our semiconductor products” and “Conditions outside the control of our independent subcontractors may impact their business operations.”

Executive Officers of the Registrant

Our executive officers and their ages are as follows:

There are no family relationships among our executive officers or between any executive officer and any of our directors.

John P. Daane has served as our President and Chief Executive Officer since November 2000 and as one of our directors since December 2000. Prior to joining us, Mr. Daane spent 15 years at LSI Logic Corporation, a semiconductor manufacturer, most recently as Executive Vice President, Communications Products Group, with responsibility for ASIC technology development and the Computer, Consumer, and Communications divisions. Mr. Daane earned his bachelors degree from the University of California, Berkeley in 1986.

Denis M. Berlan joined us in December 1989 as Vice President, Product Engineering and was named Vice President, Operations and Product Engineering in October 1994. In January 1996, he was named Vice President, Operations. In January 1997, he was named Executive Vice President and Chief Operating Officer. He was previously employed by Advanced Micro Devices, Inc., or AMD, a semiconductor manufacturer, and by Lattice Semiconductor Corporation, a semiconductor manufacturer, in engineering management capacities. Mr. Berlan received his M.S.E.E. in 1972 and Ph.D. in 1977 from the University of Grenoble in France and an M.B.A. in 1987 from the University of Santa Clara.

Erik R. Cleage joined us as International Marketing Manager in February 1986. He became Director, Japan and Asia Pacific Sales in April 1989, was appointed Vice President, Marketing in August 1990 and Senior Vice President, Marketing in January 1999. Previously, he was employed by AMD and Fairchild Semiconductor Corporation, a semiconductor manufacturer, in various positions. Mr. Cleage earned his bachelors degree from Stanford University in 1981.

John R. Fitzhenry joined us in May 1995 as Vice President, Human Resources. From February 1983 to May 1995, he was employed by Apple Computer, Inc., a manufacturer of personal computers, in various human resource management positions. Mr. Fitzhenry earned his bachelors degree from the University of California, Santa Barbara in 1971 and his J.D. from the University of the Pacific, McGeorge School of Law in 1976.

Lance M. Lissner joined us in May 1998 as Vice President of Business Development and Investor Relations and was appointed Senior Vice President, Business Development in November 2000. Prior to that time, Mr. Lissner was a corporate officer of Measurex Corporation, a developer of computer-integrated measurement, control, and information systems, where he was employed since 1973 and held various positions in sales, marketing, engineering, and business development. Mr. Lissner earned his bachelors degree from Harvey Mudd College in 1972 and his masters degree from Stanford University in 1973.

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George A. Papa joined us in February 2002 as Senior Vice President, Worldwide Sales. From February 2000 to February 2002, Mr. Papa served as Vice President of Worldwide Sales of the Communications Business Group of Marvell Semiconductor, Inc., a semiconductor company. From March 1997 to February 2000, he served as Vice President of Worldwide Sales for Level One Communications, Inc., a subsidiary of Intel Corporation, a semiconductor company. From February 1991 to March 1997, Mr. Papa served as Vice President of North American Sales for Siemens Corporation, a diversified global technology company. Mr. Papa earned his bachelors degree from Northeastern University in 1971.

Jordan S. Plofsky joined us in February 2001 as Senior Vice President, Vertical Markets and Embedded Processor Products and became Senior Vice President, Applications Business Groups in March 2002. Prior to joining us, Mr. Plofsky was employed by LSI Logic from October 1996 to February 2001, most recently as Executive Vice President, Enterprise Infrastructure Group from November 2000 to February 2001 and Vice President and General Manager, Networking Products Division from June 1998 to November 2000. Mr. Plofsky earned a bachelors degree from the University of Illinois, Urbana-Champaign in 1982.

Nathan M. Sarkisian joined us in June 1992 as Corporate Controller. He was appointed Vice President, Finance and Chief Financial Officer in August 1995 and Senior Vice President and Chief Financial Officer in March 1998. Prior to joining us, Mr. Sarkisian held various accounting and financial positions at Fairchild and at Schlumberger Limited, an oil field services company. Mr. Sarkisian earned a bachelors degree from Stanford University in 1981 and an M.B.A. from Harvard University in 1992.

Katherine E. Schuelke joined us in March 1996 as Corporate Attorney. She became Senior Corporate Attorney in July 1997 and Assistant General Counsel and Assistant Secretary in July 1999. In October 2001, she was appointed Vice President, General Counsel and Secretary. Prior to March 1996, Ms. Schuelke was an attorney at the law firm of Morrison & Foerster LLP for seven years. Ms. Schuelke earned a bachelors degree from the State University of New York at Buffalo in 1986 and a J.D. from New York University in 1989.

Employees

As of December 31, 2002, we had 1,882 regular employees. Of these employees, 1,218 were located in the United States, and 664 were employed in 17 other countries. None of our employees is represented by a labor union. We have not experienced any work stoppages, and we believe that our employee relations are good.

Additional Information

Our annual report on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and amendments to reports filed pursuant to Sections 13(a) and 15(d) of the Securities Exchange Act of 1934, as amended, are available free of charge on our website at www.altera.com, when such reports are available on the Securities and Exchange Commission website.

Item 2. Properties.

Our headquarters facility is located in San Jose, California on approximately 25 acres of land, which we purchased in June 1995. The campus for the headquarters facility currently consists of four interconnected buildings totaling approximately 500,000 square feet. Design, research, marketing, administrative, and limited manufacturing activities are performed in this facility. We also have a 240,000 square foot design and test engineering facility in Penang, Malaysia. This facility is situated on land leased on a long-term basis from the Penang Development Corporation. Finally, we lease on a short-term basis office facilities for our domestic and international sales management offices, our European Technology Center in the United Kingdom, our Toronto Technology Center, and our Ottawa Technology Center. Rental expense under all operating leases amounted to $6.3 million in 2002. We believe that our existing facilities and planned future expansions are adequate for our current and foreseeable future needs.

Item 3. Legal Proceedings

We are a party to lawsuits and have in the past and may in the future become a party to lawsuits involving various types of claims, including, but not limited to, unfair competition and intellectual property matters. Legal proceedings tend to be unpredictable and costly and may be affected by events outside of our control. We cannot assure you that litigation will not have an adverse effect on our financial position or results of operations.

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In November 1999, we sued Clear Logic Inc. in the United States District Court for the Northern District of California, San Jose Division, alleging that Clear Logic is unlawfully appropriating our registered mask work technology in violation of the federal mask work statute and that Clear Logic has unlawfully interfered with our relationships and contracts with our customers. The lawsuit seeks compensatory and punitive damages and an injunction to stop Clear Logic from unlawfully using our mask work technology and from interfering with our customers. Clear Logic answered the complaint by denying that it is infringing our mask work technology and denying that it has unlawfully interfered with our relationships and contracts with our customers. Clear Logic also filed a counterclaim against us for unfair competition under California law alleging that we have made false statements to our customers regarding Clear Logic.

In October 2001, the District Court ruled on summary judgment motions filed by both parties. The Court denied Clear Logic’s motion for summary judgment of our claim of tortious interference with our software license, ruling that “using the bitstream [from our MAX+PLUS II software] to program a Clear Logic device violates Altera’s software license.” Further, the Court granted our motion for summary judgment disposing of Clear Logic’s counterclaim of unfair competition. On January 4, 2002, Clear Logic filed a petition for Chapter 11 bankruptcy, which resulted in all proceedings in the lawsuit being automatically stayed. We moved to have this stay lifted, and the bankruptcy court granted our motion effective May 31, 2002. On July 9, 2002, the Court issued a preliminary injunction enjoining Clear Logic and its distributors from selling “any semiconductor device that was made, designed, configured, programmed or otherwise manufactured through or with the aid of any bitstream file or other output generated by” our MAX+PLUS II software. On November 25, 2002, a jury rendered a verdict in our favor on all issues in the lawsuit.

Due to the nature of the litigation with Clear Logic, our management cannot estimate the total expenses that we will incur prosecuting the lawsuit. Although we cannot make any assurances as to the results of this case, we intend to pursue our claims vigorously.

Item 4. Submission of Matters to a Vote of Security Holders.

None.

PART II

Item 5. Market for Registrant’s Common Equity and Related Stockholder Matters.

Our common stock trades on the Nasdaq National Market under the symbol “ALTR.” As of February 18, 2003, there were approximately 706 stockholders of record. However, the majority of our shares are held by brokers and other institutions on behalf of approximately 76,774 stockholders as of February 18, 2003.

The closing price of our common stock on February 18, 2003 was $12.51 per share as reported by the Nasdaq National Market. The following table sets forth, for the periods indicated, the high and low closing sale prices for our common stock as reported by the Nasdaq National Market:

Our policy has been to reinvest earnings to fund future growth and to repurchase shares of our common stock. Accordingly, we have not paid any cash dividends on our common stock and do not anticipate paying cash dividends in the foreseeable future.

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Item 6. Selected Financial Data.

The section entitled “Selected Consolidated Financial Data” in our 2002 Annual Report is incorporated herein by reference.

Item 7. Management’s Discussion and Analysis of Financial Condition and Results of Operations.

The following Management’s Discussion and Analysis of Financial Condition and Results of Operations, as well as information contained in “Risk Factors” below and elsewhere in this report, contains forward-looking statements, which are provided under the “safe harbor” protection of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally written in the future tense and/or are preceded by words such as “will,” “may,” “should,” “could,” “expect,” “suggest,” “believe,” “anticipate,” “intend,” “plan,” or other similar words. Forward-looking statements include statements regarding (1) our gross margins and factors that affect gross margins, such as the costs of raw materials, our ability to absorb manufacturing costs, trends in selling prices, and the sale of previously reserved inventory; (2) our research and development efforts; (3) the commercial success of our new products; (4) trends in future sales; (5) the availability of cash to finance operations; (6) our ability to hold our fixed income investments until maturity; and (7) future economic conditions.

Forward-looking statements are not guarantees of future performance and involve risks and uncertainties. The forward-looking statements contained in this report are based on information that is currently available to us and expectations and assumptions that we deem reasonable at the time the statements were made. We do not undertake any obligation to update any forward-looking statements in this report or in any of our other communications, except as required by law. All such forward-looking statements should be read as of the time the statements were made and with the recognition that these forward-looking statements may not be complete or accurate at a later date.

Many factors may cause actual results to differ materially from those expressed or implied by the forward-looking statements contained in this report. These factors include, but are not limited to, those risks set forth under “Risk Factors.”

Overview

We design, manufacture, and market high-performance, high-density programmable logic devices, or PLDs, pre-defined design building blocks known as intellectual property, or IP, cores, and associated development tools. Our PLDs, which consist of field-programmable gate arrays, or FPGAs, and complex programmable logic devices, or CPLDs, are semiconductor integrated circuits that are manufactured as standard chips that our customers program to perform desired logic functions within their electronic systems. Our customers can license IP cores from us for implementation of standard functions in their PLD designs. Customers can also develop, compile, verify, and program their PLD designs using our proprietary development software, which operates on personal computers and engineering workstations. FPGAs, which represented 61% of our sales in 2002, consist of our Stratix, Cyclone, APEX, APEX II, FLEX, ACEX, Excalibur, and Mercury families; and CPLDs, which represented 31% of our total sales in 2002, consist of our MAX and Classic families. The balance of our sales consists of masked devices, software tools, IP cores, and support products. Our products serve a wide range of markets, including telecommunications, data communications, computing and storage, consumer, and industrial applications.

We classify our products into three categories: New, Mainstream, and Mature and Other Products.

	•	New Products include ACEX 1K, APEX 20KC, APEX 20KE, APEX II, MAX 7000B, Cyclone, Excalibur, HardCopy, Mercury, and Stratix families;
	•	Mainstream Products include APEX 20K, FLEX 6000, FLEX 10KA, FLEX 10KE, MAX 3000A, and MAX 7000A families; and
	•	Mature and Other Products include Classic, FLEX 8000, FLEX 10K, MAX 7000, MAX 7000S, and MAX 9000 families, MPLD, configuration and other devices, tools, and intellectual property.

Critical Accounting Policies

The preparation of our financial statements and related disclosures in conformity with accounting principles generally accepted in the United States requires our management to make judgments and estimates that affect the amounts reported in our financial statements and accompanying notes. Our management believes that we consistently apply judgments and

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REVENUE RECOGNITION . We sell our products to original equipment manufacturers, or OEMs, and to electronic components distributors who resell products to OEMs or their subcontract manufacturers. We recognize revenue on products sold to OEMs upon shipment, but defer recognition of revenue on products sold to distributors until the products are resold. More than ninety-five percent of our products are sold to distributors for subsequent resale to OEMs or their subcontract manufacturers. Our revenue reporting is highly dependent on receiving pertinent and accurate data from our distributors in a timely fashion. Distributors provide us periodic data regarding the product, price, quantity, and end customer on their shipments as well as the quantities of our products they still have in stock. Using this reported information, we apply judgment in reconciling changes in distributors’ inventories of our products to their reported activities. We have developed robust systems for receiving that information and have additionally developed cross-checks for verifying the accuracy of the reported information. In addition, we perform audits of our distributors’ information systems and inventories. We believe that the information supplied to us by our distributors is materially accurate and complete. If distributors incorrectly report their sales or mis-state their inventory of our products, it could lead to inaccurate reporting of our revenues and income.

VALUATION OF INVENTORIES . Inventories are recorded at the lower of cost on a first-in-first-out basis (approximated by standard cost) or market. We reserve inventory that is excess to projected customer demand, and the creation of such reserves results in a write-down of inventory to net realizable value and a charge to cost of goods sold. Historically, it has been difficult to forecast customer demand especially at the part-number level. Many of the orders we receive from our customers and distributors request delivery of product on relatively short notice and with lead times less than our manufacturing cycle time. In order to provide competitive delivery times to our customers, we build and stock a certain amount of inventory in anticipation of customer demand that may not materialize. Moreover, as is common in the semiconductor industry, we allow customers to cancel orders with minimal advance notice. Thus, even product built to satisfy specific customer orders may not ultimately be required to fulfill customer demand. We routinely compare our inventory against projected demand and as a result frequently record immaterial inventory charges to provision for excess and obsolete inventories. Nevertheless, at any point in time, some portion of our unreserved inventory is subject to the risk of being materially in excess to projected demand. In 2001, as a result of a large and unforecasted decline in sales, we determined that a significant portion of our inventory was excess to projected demand and recorded inventory charges of $154.5 million. While we endeavor to accurately predict demand and stock commensurate inventory levels, we may record unanticipated material inventory write-downs in the future.

VALUATION OF PROPERTY, EQUIPMENT AND INTANGIBLE ASSETS . We evaluate the recoverability of our property, equipment and intangible assets in accordance with Statement of Financial Accounting Standards No. 144, or SFAS No. 144, “Accounting for the Impairment or Disposal of Long-Lived Assets.” We regularly compare the carrying value of long-lived assets to our projection of future undiscounted cash flows attributable to such assets and in the event that the carrying value exceeds the future undiscounted cash flows, we record an impairment charge against income equal to the excess of the carrying value over the asset’s fair value. Actual useful lives and future cash flows could be different from those estimated by our management. These differences could have a material effect on our future operating results.

In 2001, we recorded a charge of $13.3 million for the impairment of (1) production and other equipment that was removed from service and subsequently sold, (2) purchased intangible assets related to technology acquired in previous acquisitions but no longer being used, and (3) investments in development stage enterprises that were in financial distress. These charges were classified as operating expenses in our consolidated statements of operations.

Results of Operations

SALES : Sales were $711.7 million in 2002, $839.4 million in 2001, and $1,376.8 million in 2000. Sales declined 15% in 2002 from 2001 and 39% in 2001 from 2000.

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The decline in sales in 2001 was the result of five consecutive sequential declines in quarterly sales beginning in the fourth quarter of 2000 and ending in the fourth quarter of 2001. The protracted deceleration resulted in a peak-to-trough decline in quarterly sales of nearly 60%. This period of decline was the result of a general economic downturn and softening demand for products manufactured by our customers, especially those in the communications and computing equipment markets. Our customers, in response to reduced demand for their products, acted to reduce their inventories resulting in an inventory contraction throughout the entire supply chain. The reduction in end-market demand coupled with the inventory contraction resulted in significant sales declines for the semiconductor industry including the programmable logic segment.

As the rate of decline in our customers’ markets moderated and as customers achieved reduced inventories consistent with their reduced sales levels, they began to procure more semiconductors, including our products. This increase in demand, coupled with increasing sales of our New Products, led to sequential quarterly sales increases during 2002. Sales in total decreased 15% in 2002 compared to 2001 primarily due to lower unit sales of our Mature and Mainstream products as well as lower average unit selling prices in all product categories.

Sales by product category, as a percentage of total sales, were as follows for 2002, 2001, and 2000:

New Products represented 27% of total sales in 2002, up from 13% of total sales in 2001. Our New Products have been developed and introduced to the marketplace over the last several years. These products have additional features and higher densities than their predecessors. As a result of increased customer demand for PLDs, with higher densities and enhanced performance, we have experienced a shift in sales to our newer products from our more mature products. Sales of New Products increased 75% in 2002 compared to 2001, and 113% in 2001 compared to 2000. We expect that sales of our New Products will continue to increase in 2003 as design win momentum in our New Products continues to be strong.

Sales of Mainstream Products declined 28% in 2002 compared to 2001 and 42% in 2001 compared to 2000. Sales of Mature and Other Products declined 30% in 2002 compared to 2001 and 48% in 2001 compared to 2000. The declines in both product categories for 2002 and 2001 were driven by continued softness in end-markets, discontinuation of certain product lines by some customers, excess inventory at various customers, as well as price declines.

The semiconductor industry is intensely competitive and our products are subject to price erosion. New products generally have higher selling prices that typically decline over a product’s life cycle. Our strategy is to offset the overall reduction in sales that results from declining selling prices by introducing new products. This strategy is dependent on successful development and roll-out of new products and the market’s acceptance of those products. We believe that we have been generally successful in that regard, but can give no assurance of future success. Unless future new products are developed and introduced in a timely fashion and achieve market acceptance, future sales will decline.

Effective January 1, 2002, we adopted a new methodology for revenue classification by market segment. The market segment data is derived by analysis that involves interpretation and extrapolation and relies on information provided to us by our distributors and end customers; actual percentages may be different. Sales by market segment, as a percentage of total sales, were as follows for 2002. Comparable data for prior years is not available.

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Sales in the Communications market segment declined 1% in the fourth quarter of 2002 compared to the same period a year ago. For the same periods, Industrial and Automotive increased 22%, Computer and Storage increased 13%, and Consumer increased 36%. The increase in the Industrial and Automotive market segment was primarily due to growth in medical business and manufacturing and test and measurement equipment. The increase in the Consumer market segment was primarily due to growth in the digital broadcast business.

Despite the unfavorable economic conditions and reduced capital spending for communications equipment, we continued to generate the largest percentage of our sales from the Communications market segment. The Communications market segment includes the networking, telecommunications, and wireless sectors. We believe that the Communications market segment will continue to be our largest market segment for the foreseeable future.

Sales by geography, as a percentage of total sales, were as follows for 2002, 2001, and 2000:

North America sales represented 40% of total sales in 2002 compared to 45% in 2001 and 57% in 2000. In large part, the percentage of sales for North America declined as certain end customers shifted their production from North America to subcontract manufacturing sites located in Asia Pacific. We expect that sales will continue to transfer from North America, Europe, and Japan to Asia Pacific for the foreseeable future. In absolute dollars, North America sales declined 25% in 2002 from 2001, while sales in Europe declined 22%, and Japan declined 8%. The declines in sales were primarily due to a general economic downturn and softening end-market demand especially in the Communications and Computer and Storage sectors.

In 2001, North America sales declined 52% from 2000, while sales in Europe declined 28%, Japan declined 20%, and Asia Pacific declined 6%. The decreases in sales in all geographical locations were primarily a result of unfavorable economic conditions that began to affect us in November 2000.

Major items in the statements of operations, expressed as a percentage of sales, were as follows: