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SECURITIES AND EXCHANGE COMMISSION

Form 10-K

000-31311

PDF SOLUTIONS, INC.

(408) 280-7900

Securities registered pursuant to Section 12(b) of the Act:

Securities registered pursuant to Section 12(g) of the Act:

      Indicate by check mark whether the Registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days.     Yes þ          No o

      Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K.     o

      The aggregate market value of the voting stock held by non-affiliates of the Registrant was approximately $197,912,074 as of March 25, 2002, based upon the closing sale price on the Nasdaq National Market reported for such date. Shares of Common Stock held by each officer and director and by each person who owns 5% or more of the outstanding Common Stock have been excluded in that such persons may be deemed to be affiliates. This determination of affiliate status is not necessarily a conclusive determination for other purposes.

      There were 22,900,051 shares of the Registrant’s Common Stock issued and outstanding as of March 25, 2002.

DOCUMENTS INCORPORATED BY REFERENCE

      Part III incorporates information by reference from the definitive proxy statement for the Annual Meeting of Stockholders to be held on May 17, 2002.

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TABLE OF CONTENTS

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PART I

Item 1.     Business.

Overview

      Our comprehensive technologies and services enable semiconductor companies to improve yield and performance of ICs by providing infrastructure to integrate the design and manufacturing processes. We believe that our solutions significantly improve a semiconductor company’s time to market, the rate at which yield improves and product profitability. Our solutions combine proprietary manufacturing process simulation software, yield and performance modeling software, comprehensive test chips, proven yield and performance enhancement methodologies, and professional services. The result of implementing our solutions is the creation of value that can be measured based on improvements to our customers’ actual yield. We align our financial interests with the demonstrated yield and performance improvement realized by our customers and receive revenue based on this value. To date, we have sold our technologies and services to key semiconductor companies including leading integrated device manufacturers such as Toshiba Corporation, Matsushita Electric Industrial Co., and Sony Corporation.

Industry Background

      Integrated circuits, or ICs, are critical components used in an increasingly wide variety of applications, such as computer systems; Internet and communications infrastructure equipment, such as wireless and network devices; and consumer products, such as cellular phones, pagers, personal digital assistants, game consoles and network appliances. As IC performance has increased and size and cost have decreased, the use of ICs in these applications has grown significantly. A large part of this growth is expected to occur in deep submicron ICs having circuit component feature sizes, or geometries, that measure less than 0.20 microns, or millionths of a meter. ICs are manufactured onto silicon disks, commonly referred to as wafers. Rapid technological innovation has shortened product life cycles, which fuels the economic growth of the semiconductor industry.

      Customers for electronic products continue to demand new applications with more power, reduced cost and smaller size. As a result, IC companies are adopting new designs, process technologies and materials at an unparalleled rate. For example, silicon germanium processes will be integrated with standard logic processes to provide better performance for radio-frequency components in communication ICs.

      In addition, the IC industry faces compression in product lifecycles. Previously, companies could afford to take months, or years in some cases, to integrate new designs with manufacturing processes. With historically longer product life cycles, IC companies ramped production slowly, produced at high volume once the product hit its prime, and slowly reduced production volume when the price and the demand started to decrease near the end of a product’s life cycle. More recently, demand — largely driven by consumers in search of the next, more powerful, smaller device — has dramatically reduced the time that semiconductor companies have to successfully bring a product to market in high volumes. Companies now need to sell the most volume when a product is first introduced and has a performance and pricing advantage over its competition, or they will lose the market opportunity and the related high revenue.

      Increased IC complexity and compressed product lifecycles create significant challenges to achieving competitive initial yields and optimizing performance. Yield is the percentage of ICs produced that meet customers’ specifications and initial yield is specifically the percentage of good ICs produced when volume production first commences. For example, it is not uncommon for an initial manufacturing run to yield only 20%, meaning 80% of those wafers were wasted. Yield improvement and performance optimization are critical drivers of IC companies’ financial results because they typically lead to cost reduction and revenue generation concurrently, causing a leveraged effect on profitability. Historically, yield loss resulted primarily from

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	•	systematic yield loss, or non-functioning ICs resulting from the lack of compatibility between the design and manufacturing processes; and
	•	performance yield loss, or functioning ICs that do not meet customer speed requirements.

      Manufacturers have historically addressed systematic and performance yield loss reactively and almost exclusively by inefficient and time consuming trial-and-error adjustments to the manufacturing process during volume production.

      Disaggregation of the semiconductor industry has further complicated IC companies’ ability to maximize initial yields. Historically, leading semiconductor companies designed, manufactured and tested their ICs internally, thus retaining process-design integration know-how. Today, the industry is comprised of separate organizations, as well as separate companies, that specialize in a particular phase of designing and manufacturing ICs. This has fragmented the knowledge related to the integration of IC design and manufacturing and resulted in great difficulty in making designs compatible with a manufacturing process prior to volume production.

      The combination of increasingly complex ICs and design and manufacturing processes, reduced time to produce new products in high volumes and the loss of information due to disaggregation has left a gap between the design of an IC and its manufacture. We call this gap the Design-to-Silicon-Yield^TM gap. This gap creates a number of significant problems for semiconductor companies, including:

	•	Slow Yield Ramp. Increased process and design complexity extends the time needed to arrive at acceptable yields and increases the time it takes for a semiconductor company to begin producing at high volumes, directly and negatively impacting a company’s potential market share and potential revenue.
	•	Longer Time to Market and Increased Up-front Costs. Yield problems in the initial manufacturing phase result in numerous design and process iterations that delay product introductions and appreciably increase up-front costs, such as non-recurring engineering, mask-set redesigns and excessive sample wafers.
	•	High Cost of Goods Sold. Processed wafer costs are typically the largest component of an IC company’s cost of goods sold and, therefore, yield loss significantly increases costs.
	•	Difficulties Producing High-Performance ICs. High-performance ICs are particularly sensitive to the lack of compatibility between design and manufacturing. In addition, semiconductor companies typically experience a trade-off between yield and IC performance because it is generally more difficult to produce ICs with more stringent specifications. Semiconductor companies may target high-performance ICs because they typically have higher margins.

      Delivering complex ICs quickly and in high volumes requires unique silicon infrastructure solutions to tightly integrate the IC design and manufacturing processes — thus bridging this Design-to-Silicon-Yield gap.

The PDF Solution

      We provide comprehensive silicon infrastructure technologies and services to integrate an IC design with its manufacturing processes, thereby bridging the Design-to-Silicon-Yield gap. Our solution combines proprietary manufacturing process simulation software, yield and performance modeling software, comprehensive test chips, proven yield and performance enhancement methodologies and professional services to increase yield, accelerate yield ramp and improve IC performance. We create an analysis of yield loss mechanisms to identify, quantify and correct the issues that cause yield loss, often before an IC design is complete. This drives IC design and manufacturing improvements that enable our customers to have higher initial yields and achieve and exceed targeted IC yield and performance throughout product life cycles. Our solution is designed to increase the initial yield when a design first enters a manufacturing line, increase the rate at which that yield

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      The key benefits of our solution to our customers are:

      Faster Time to Market. Our Design-to-Silicon-Yield solutions are designed to significantly accelerate our customers’ time to market and increase product profitability. Our solutions, which predict and improve product yield even before IC product design is complete, change the traditional design-to-silicon sequence to primarily a concurrent process, and decrease our customers’ time to market. Systematically incorporating knowledge of the integration of the design and manufacturing processes into software modules, enables faster introduction of additional products with consistently high initial yields. Our solutions decrease design and process iterations, reduce our customers’ up-front costs and speed time to market, thus providing our customers with early-mover advantages such as increased market share and higher selling prices.

      Faster Time to Volume. After achieving higher initial yields and faster time to market, our solutions are designed to enable our customers to isolate and eliminate remaining systematic yield issues to achieve cost efficient manufacturing volume. Once a manufacturing process has been modeled using our solutions, our customers are able to diagnose problems and simulate potential corrections more quickly than using traditional methods. In addition, if process changes are required, improvements can be verified more quickly using our technology than using traditional methods. Our Design-to-Silicon-Yield solutions enable our customers to quickly reach cost efficient volume, so that they are able to increase revenue, improve their competitive position, and capture higher market share.

      Increased Manufacturing Efficiencies. After using our solutions for product introduction and yield ramp, our solutions are designed to allow our customers to achieve a higher final yield and therefore a lower cost of goods sold. In addition, our Design-to-Silicon-Yield solutions are designed to provide our customers with the ability to proactively monitor process health to avoid potential yield problems. By paying us gain share as our customers recognize cost savings from these manufacturing efficiencies, they also benefit from better matching their costs to their revenue.

      Increased Semiconductor Performance. Our Design-to-Silicon-Yield solutions are designed to enable our customers to achieve over-all higher level semiconductor performance by modeling the factors that affect speed and simulating possible improvements. Typically, the changes necessary to achieve higher performance result in an overall reduction in yield. Because our solutions also model the factors that affect yield at the same time, our customers can often achieve both higher IC performance and higher yield, thereby generating higher margin revenues.

Our Strategy

      Our objective is to provide the industry standard in silicon infrastructure technologies and services for integrating IC designs and manufacturing processes. Key elements of our strategy include:

      Leverage Our Innovative Gain Share Business Model. We intend to expand the gain share component of our customer contracts. We believe this innovative approach helps us to form highly collaborative and longer-term relationships. Working closely with our customers on their core technologies with a common focus on their business results provides direct and real-time feedback, which we will continue to use to rapidly generate market-driven improvements that add value to our solutions. We also believe that gain share allows us to increase penetration of our customer accounts because adding new semiconductor products to existing lines is increasingly easy and economical for our customers once our Design-to-Silicon-Yield solutions are implemented. As our gain share customers succeed in improving their yield and performance while reducing costs, we believe that we will generate new customer accounts based on these successes.

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      Focus on Key IC Product Segments. We intend to focus our solution on key IC product segments such as system-on-a-chip, communications networking, graphics and high-performance central processing units. These are high-volume, high-growth segments and are fueled by the growth of Internet and wireless infrastructure and consumer applications. As a result, we will expand our solution for key technology drivers such as low-k dielectrics, copper, embedded DRAM and silicon germanium, which are all somewhat new and relatively complex manufacturing process technologies. We believe that these product segments are particularly attractive because they include complex IC design and manufacturing processes where processed silicon is costly and yield is critical.

      Expand Strategic Relationships with Industry Leaders. We intend to continue to extend and enhance our relationships with leading companies at key stages of the design-to-silicon process, such as manufacturing equipment vendors, silicon intellectual property vendors, semiconductor foundries, and test and assembly equipment providers. We believe that strategic relationships with industry leaders will increase our insight into future industry needs, thus allowing us to further accelerate our learning and enhance the value of our solutions. We expect these relationships to also serve as sales channels for our Design-to-Silicon-Yield solutions and to increase industry awareness of our solutions.

      Extend Our Technology Leadership Position. We intend to continue expanding our research and development efforts by leveraging our experienced engineering staff and codifying the knowledge that we continually acquire in our solution implementations. In addition, we intend to selectively acquire complementary businesses and technologies to increase the scope of our solutions. We will continue to make significant investments in the development of proprietary manufacturing process simulation software, yield and performance modeling software, other technologies, and yield and performance enhancement methodologies to accommodate our customers’ increasingly complex semiconductor needs.

      Expand Worldwide Presence. We intend to establish engineering design and product development centers in key international locations around the world. To date, we have focused on regions specific to our design efforts — the United States, Japan and Europe. We intend to expand geographically to gain access to international engineering talent and to maintain proximity to our expanding customer base. In addition, we believe that these efforts will have collateral sales and marketing benefits as a result of local presence.

Technology

      Our Design-to-Silicon-Yield solutions combine proprietary manufacturing process simulation, yield and performance modeling software, comprehensive test chips and proven yield and performance enhancement methodologies. To calculate the likely yield of an IC design, we have designed a proprietary, patent-pending system that uses each of these technologies to:

	•	identify yield-relevant layout pattern elements by using the knowledge base embedded in our technologies;
	•	categorize IC layout components into these elements;
	•	quantify the yield of each of the elements; and
	•	model the frequency of yield-relevant elements and their yield-loss probabilities.

      We continually enhance our technologies through the codification of knowledge that we gain in our solution implementations.

      Our software incorporates the following elements:

	•	efficient modeling algorithms of the interaction between design layout and manufacturing processes, which creates layout pattern-dependent systematic yield models that encompass process technologies such as lithography, etch, interlayer dielectric chemical-mechanical polishing (ILD CMP), copper CMP and shallow trench isolation CMP (STI CMP);
	•	pattern recognition algorithms, which allow us to categorize the yield-relevant elements of a design as a function of their layout, including the effects of their proximity to other elements;

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	•	a hierarchical representation of the layout, which encompasses layout manufacturing process proximity effects and minimizes the time necessary for computation of systematic yield prediction;
	•	algorithms that compute an overall yield impact matrix for design as a function of layout elements and manufacturing yield models; statistical simulation of circuit performance as a function of manufacturing process variations, including their impact on transistor performance; and
	•	statistical process and device simulation.

      Our software that is used to predict yields of designs is also used to generate our proprietary Characterization Vehicle^TM test chips. These Characterization Vehicle, or CV^TM, test chips are used to calibrate the yield and to provide manufacturers with early prediction of product yields, often before the IC design is completed. Early prediction generated by the CV test chips is the basis of the yield improvement methodologies for the manufacturing line. Information generated by the CV test chips is also used to improve the IC design.

      Our methodologies are a series of guidelines that our implementation teams use to drive our customers’ adoption of our software and CV test chips to quantify the yield impact of each module of the process and design block, simulate the impact of changes to the design and manufacturing process, and analyze the outcome of executing such changes.

Products and Services

      Our Design-to-Silicon-Yield solutions consist of integration engineering services, proprietary software and other technologies. Our proprietary software and other technologies include proprietary manufacturing process simulation software, yield and performance modeling software, and comprehensive CV test chips.

      We tailor our solution to our customers’ specific business issues by offering one of the following Design-to-Silicon-Yield solutions:

	•	Integration and Ramp. This solution enables our customers to ramp the yield of new products when the manufacturing process or fabrication facility is still being completed or is new. Our solution is used to improve the process capability and manufacturability of designs targeted for that process.
	•	Yield and Performance Ramp. This solution enables our customers to ramp the yield and performance of new products when the manufacturing process is assumed to be mostly correct and complete. In this case, we focus mostly on design oriented issues.
	•	Design-Based Yield ImprovementTM. This solution enables our customers to optimize the manufacturability of their IC products by improving the compatibility of their designs with a third party’s manufacturing process. In this case, we focus on design oriented issues.

      Our Design-to-Silicon-Yield solutions can incorporate various software and other technologies, typically including the following:

	•	Characterization Vehicle Test Chips and Software. Our integration engineers develop a design of experiments, or DOE, to determine how IC design building blocks interact with the manufacturing process. Our CV software utilizes the DOE, as well as a library of these building blocks that we know have potential yield and performance impact, to generate comprehensive Characterization Vehicle test chips. These CV test chips are run through the manufacturing process with intentional modifications to explore the effects of natural manufacturing process variations. Our CV analysis software is then used to analyze the electrical test results generated by the test chips to model the yield and performance effects of process variations on these design building blocks.
	•	pdExTM. pdEx analyzes an IC design to compute its systematic and contamination yield loss. pdEx takes as input, a layout that is typically in industry standard format, proprietary yield models generated by running our CV test chips, and other test chip and in-line inspection data. pdEx is designed to estimate the yield loss due to optical proximity effects, etch micro loading, dishing in chemical-mechanical polishing and contamination, as well as a number of other basic process issues.

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	•	Circuit Surfer® Software. Our Circuit Surfer software estimates the performance yield and manufacturability of small blocks in a design, such as analog subsystems or critical paths of digital blocks. Using our Circuit Surfer software, a design engineer is able to estimate how manufacturing process variations will impact circuit performance.
	•	pdFab® Software. Our pdFab software provides a framework for statistical manufacturing process and transistor simulation that enables our integration engineers to understand the effects of expected or measured manufacturing process variations on transistor performance. pdFab is used to optimize the transistor architecture and associated manufacturing process, and is primarily targeted to provide higher IC performance, although yield improvements may also be generated.
	•	OptissimoTM Software. Our Optissimo software is used to optimize the layout of a design to minimize the impact of wafer printing variations due to optical proximity effects. Optissimo can be used for model based optical proximity correction technologies.

      While the primary distribution method for our software and technologies is through our Design-to-Silicon-Yield solutions, we have in the past and may in the future separately license these and other technologies.

Customers

      Our current customers are primarily large integrated device manufacturers, or IDMs. We have established ongoing relationships with key IDMs such as Toshiba Corporation, Matsushita Electric Industrial Co., Sony Corporation, Conexant Systems, Inc., and Philips Semiconductor. Our customers’ targeted product segments vary significantly, including microprocessors, graphics, memory, and communications. We believe that the adoption of our solutions by such diverse and technologically advanced companies validates the application of our Design-to-Silicon-Yield solutions to the broader market.

      Toshiba and Matsushita represented 34% and 29%, respectively, of our total revenue for the year ended December 31, 2001. Toshiba, Sony, Conexant, and Philips represented 32%, 27%, 15% and 10%, respectively, of our total revenue for the year ended December 31, 2000. Toshiba, Fujitsu Limited and Sony represented 53%, 19% and 15%, respectively, of our total revenue for year ended December 31, 1999. No other customer accounted for 10% or more of our revenue in 2001, 2000, or 1999.

Sales and Marketing

      Our sales strategy is to pursue targeted accounts through a combination of our direct sales force and strategic alliances. To date, we have targeted leading IDMs to validate our solutions in leading technology and manufacturing environments and to establish credibility to support future sales and marketing efforts. We have recently extended these efforts to other IDMs and fabless semiconductor companies. For sales in the United States, we rely on our direct sales team, which primarily operates out of our San Jose, California headquarters. In Japan, we use our direct sales team as well as Innotech Corporation, a large semiconductor sales and distribution company located in Japan. Innotech has been instrumental in providing introductions to key executives with some of our targeted customers, which has allowed us to establish direct relationships with these key executives. We expect to continue establishing strategic alliances with vendors in the electronic design automation software, capital equipment for IC production, silicon intellectual property and mask-making software segments to create and take advantage of co-marketing opportunities. We believe that these relationships will also serve as sales channels for our Design-to-Silicon-Yield solutions and to increase industry awareness of our solutions.

      We strive to provide compelling value in our initial engagement to establish ourselves as a key vendor to our customers and solidify relationships at the executive level. Early in the solution implementation, our engineers establish relationships across the organization and gain a solid understanding of our customers’ business issues. Our direct sales and solution implementation teams combine their efforts to deepen our customer relationships by expanding our penetration across the customer’s products, processes and technologies. This close working relationship with the customer has the added benefit of helping us identify new

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Research and Development

      Our research and development focuses on rapidly developing and introducing new proprietary technologies, software products and enhancements to our existing solutions. We use a rapid-prototyping paradigm in the context of the customer engagement to achieve these goals. In addition, we have a highly-qualified technical advisory board comprised of professors from Harvard University’s Business School, the Massachusetts Institute of Technology, Carnegie Mellon University and the University of California, Berkeley to help us develop and guide our strategic development roadmap.

      We have made and expect to continue to make substantial investments in research and development. The complexity of our Design-to-Silicon-Yield technologies requires expertise in physical IC design and layout, transistor design and semiconductor physics, semiconductor process integration, numerical algorithms, statistics, and software development. We believe that the multidisciplinary expertise of our team of engineers will continue to advance our market and technological leadership. We conduct extensive in-house training for our engineers in the technical areas, as well as focusing on ways to enhance client service skills. At any given time, about one quarter of our research and development engineers are operating in the field, partnered with solution implementation engineers in a deliberate strategy to provide direct feedback between technology development and client needs. Our research and development expenses were approximately $12.2 million in 2001, $6.4 million in 2000 and $3.1 million in 1999.

Competition

      The semiconductor industry is highly competitive and characterized by rapidly changing design and process technologies, evolving standards, short product life cycles and decreasing prices. While the market for silicon infrastructure is in its infancy, it is rapidly evolving and we expect competition to develop and continue to increase. We believe a comprehensive solution to quickly close the Design-to-Silicon-Yield gap requires a unified system of yield models, design analysis software, and comprehensive CV test chips. Currently, we are the only provider of comprehensive commercial solutions for integrating design and manufacturing processes. We face indirect competition from internal groups at IC companies that use an incomplete set of components, that is not optimized to accelerate their process-design integration. Some providers of yield management software or inspection equipment may seek to broaden their product offerings and compete with us. For example, KLA-Tencor has announced adding the use of test structures to one of their inspection product lines. Additionally, HPL Technologies, through its acquisition of Test Chip Technologies, has indicated its intent to further utilize test chips in its product offering. Companies such as these and those in electronic design automation could expand their offerings to include design and additional elements of the manufacturing processes and become direct competitors to us.

      We believe that the principal factors affecting competition in our market are:

	•	demonstrated results and reputation;
	•	strength of core technology;
	•	ability to implement solutions for new technology and product generations;
	•	time to market; and
	•	strategic relationships.

      Although we believe that our solutions compete favorably with respect to these factors, our market is relatively new and is evolving rapidly. We may not be able to maintain our competitive position against current and potential competitors, especially those with significantly greater resources.

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Intellectual Property

      Our future success and competitive position are dependent upon our continued ability to develop and protect proprietary software and other technologies. We rely primarily on a combination of contractual provisions, confidentiality procedures, trade secrets, and patent, copyright and trademark laws to protect our proprietary technologies and prevent competitors from using our technologies in their products. As of December 31, 2001 we have been issued one German patent and have eleven patent applications currently pending in the United States. We intend to prepare additional patent applications for submission to the United States Patent and Trademark Office. In the future, we may seek additional patent protection when we feel it is necessary.

      We license our products and technologies pursuant to non-exclusive license agreements which impose restrictions on customer use. In addition, we seek to avoid disclosure of our trade secrets, including, requiring employees, customers and others with access to our proprietary information to execute confidentiality agreements with us and restricting access to our source code. We also seek to protect our software, documentation and other written materials under trade secret and copyright laws. Despite this protection, unauthorized parties may copy aspects of our current or future software and other technologies or obtain and use information that we regard as proprietary.

      The semiconductor industry is characterized by vigorous protection and pursuit of intellectual property rights or positions. There are also numerous patents in the semiconductor industry and new patents are being issued at a rapid rate. It is also possible that third parties will claim that we have infringed their patents and current or future products. Any claims, with or without merit, could be time-consuming, result in costly litigation, cause delays, or require us to enter into royalty or licensing agreements, any of which could harm our business. Patent litigation in particular has complex technical issues and inherent uncertainties. In the event an infringement claim against us was successful and we could not obtain a license on acceptable terms or license a substitute technology or redesign to avoid infringement, our business would be harmed.

      PDF Solutions®, Circuit Surfer® and pdFab® are our registered trademarks and Characterization Vehicle^TM, CV^TM, Design-Based Yield Improvement^TM, Design-to-Silicon-Yield^TM, pdEx^TM and Optissimo^TM are trademarks of PDF. All other brand names or trademarks appearing in this document are the property of their respective holders.

Employees

      As of December 31, 2001, we had 197 employees, including 71 in client service teams, 88 in products and methods, 15 in sales and marketing and 23 in general and administrative functions. 138 of these employees are located in San Jose/ San Diego, California, 18 are located in Texas and Virginia, 27 are located in Germany, 8 employees are located in Japan and 6 employees are located in Italy. Of our 197 total employees, 163 are engineers, 133 of which have advanced degrees including 79 with Ph.Ds.

      None of our employees are represented by a labor union or are subject to a collective bargaining agreement. We believe our relationship with our employees is good.

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Executive Officers

      The following table and notes set forth information about our executive officers as of December 31, 2001:

      John K. Kibarian, Ph.D., one of our founders, has served as President since November 1991 and has served as our Chief Executive Officer since July 2000. Mr. Kibarian has served as a director since December 1992. Mr. Kibarian received a B.S. in Electrical Engineering, a M.S. E.C.E. and a Ph.D. E.C.E. from Carnegie Mellon University.

      Thomas F. Cobourn, Ph.D., one of our founders, has served in Vice Presidential capacities since June 1992 including currently as Vice President, Yield Analysis. Mr. Cobourn received a B.S., Computer Science and Engineering from the University of Pennsylvania and a M.S. E.C.E. and Ph.D. E.C.E. from Carnegie Mellon University.

      Bruce J. Hansen, has served as Vice President, Products and Methods, since July 2001. From 1988 to 2001, Mr. Hansen served as a consultant at high technology consulting organizations including PRTM (1999 to 2000) and Thomas Group (1988-1996, 2001), where he was a senior partner. From 1996 to 1999, Mr. Hansen led product development as Director of Technology Management at National Semiconductor. He also held vice president positions at Triad Systems and Motorola Corporation. Mr. Hansen received a B.S. in Electrical Engineering from the University of California, Berkeley and a M.S. in Electrical Engineering from the University of California, Irvine.

      David A. Joseph has served as Executive Vice President, Sales, Marketing, and Business Development since August 2001. He served as Vice President, Products and Methods from July 1999 through August 2001 and as Vice President, Business Development from November 1998 through June 1999. From February 1978 to October 1998, Mr. Joseph served KLA/Tencor, a semiconductor manufacturing company, in various positions, including as Japan Business Manager, VP Customer Satisfaction and GM Yield Analysis Software. Mr. Joseph received a B.S. in Mathematical Science from Stanford University.

      P. Steven Melman has served as Chief Financial Officer and Vice President, Finance and Administration since July 1998. From April 1997 to June 1998, Mr. Melman served as Vice President Finance and Administration with Animation Science Corporation, an animation company. From April 1995 to April 1997, he served as Vice President, Finance and Chief Financial Officer with Business Resource Group, a facilities management and commercial furnishings company. Mr. Melman received a B.S. in Business Administration from Boston University. Mr. Melman is a Certified Public Accountant.

      Kimon Michaels, Ph.D., one of our founders, has served in Vice Presidential capacities since March 1993 including currently as Vice President, Integration Practice, and as a director since November 1995. He also served as Chief Financial Officer from November 1995 to July 1998. Mr. Michaels received a B.S. in Electrical Engineering, a M.S. E.C.E. and a Ph.D. E.C.E. from Carnegie Mellon University.

      P.K. Mozumder, Ph.D. has served as Vice President, Integration Practice since May 1998. From June 1994 to May 1998, Mr. Mozumder served as a Branch Manager with Texas Instruments, Inc., a consumer

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      W. Steven Rowe has served as Vice President, Human Resources since February 2000. From June 1995 to February 2000, Mr. Rowe served as Vice President, Human Resources at Trident Microsystems, a multimedia semiconductor company. From May 1994 to June 1995, he served as Vice President, Human Resources at OPTi Inc., a semiconductor company. Mr. Rowe received a M.A. in Education Administration from San Jose State University, a M.A. in Speech Pathology from Chico State University and a J.D. from Lincoln University. Mr. Rowe has resigned from his position effective March 15, 2002.

      David Tarpley has served as Vice President, Worldwide Sales since November 1996. From 1995 through September of 1996, Mr. Tarpley served as Vice President, International Sales for Anagram, Inc., an Electronic Design Automation company. From 1993 to 1995, Mr. Tarpley served as Vice President, Worldwide Sales with HLD, Inc., an electronic design automation company. Mr. Tarpley received a B.S. in Business Administration from The University of California, Berkeley and an M.B.A. from The California State University Fullerton.

Item 2.     Properties.

      Our principal executive offices are located in San Jose, California where we lease approximately 18,000 square feet under a lease that expires in October 2004 and have leased an additional 18,000 square feet under a lease that will expire in May 2003. We lease 5,418 square feet in Dallas, Texas under a lease that expires in July 2002. In addition, we lease 4,200 square feet in Munich, Germany, 1,600 square feet in Tokyo, Japan and 1,665 square feet in DesEnzano, Italy under leases that expire in June 2002, April 2002 and September 2006. We believe that our current facilities in San Jose are adequate to meet our needs through May 2003, at which time we will need to obtain additional space in the San Jose area, which we expect to be able to obtain when necessary. In addition we believe that we will be able to replace all space coming off lease in 2002.

Item 3.     Legal Proceedings.

      We are not currently party to any material legal proceedings. In May 2001, we were named as a defendant in a lawsuit claiming, among other things, that we misappropriated trade secrets in connection with hiring an employee. We are defending ourselves against the claims, which we believe to be without merit. We do not believe that this litigation, or resolution of this litigation, will have a material negative impact on our business.

Item 4.     Submission of Matters to a Vote of Security Holders.

      No matters were submitted to a vote of our stockholders during the fourth quarter of fiscal 2001.

PART II

Item 5.     Market for Registrant’s Common Equity and Related Stockholder Matters.

      Our common stock has traded on The Nasdaq National Market under the symbol “PDFS” since our initial public offering on July 26, 2001. As of March 25, 2002 we had approximately 258 stockholders of record and the closing price of our common stock was $16.62 per share as reported by The Nasdaq National Market.

      The following table sets forth for the periods indicated the high and low closing sale prices for our common stock as reported by The Nasdaq National Market:

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      No cash dividends were declared or paid in fiscal 2001. We currently intend to retain all available funds to finance future internal growth and product development and do not anticipate paying any cash dividends on our common stock for the foreseeable future.

     Use of Proceeds

      Our Registration Statement on Form S-1 (File No. 333-43192) related to our initial public offering was declared effective by the SEC on July 26, 2001. The public offering commenced on July 27, 2001. All 4,500,000 shares of common stock offered in the final prospectus, as well as an additional 675,000 shares of common stock subject to the underwriters’ over-allotment option, were sold at the closing on August 1, 2001 at a price to the public of $12.00 per share (before deducting underwriting discounts and commissions) through a syndicate of underwriters managed by Credit Suisse First Boston Corporation, Robertson Stephens, Inc. and Dain Rauscher Incorporated. The aggregate gross proceeds of the shares offered and sold was $62.1 million, out of which we paid an aggregate of $4.3 million in underwriting discounts and commissions to the underwriters. In addition, as of December 31, 2001, we had incurred additional expenses of approximately $1.3 million in connection with the offering, which when added to the underwriting discounts and commissions paid by us, amounts to total estimated expenses of $5.6 million. We estimate there are no remaining outstanding invoices.

      We incurred legal expenses payable to Orrick, Herrington & Sutcliffe LLP in connection with the initial public offering of our common stock. Peter Cohn, our Secretary, is a partner in that law firm. Other than such payments, none of the net proceeds were paid, and none of the initial public offering expenses related to any payments, directly or indirectly, to directors, officers or general partners of PDF or its associates, persons owning 10% or more of any class of securities of PDF, or affiliates of PDF.

      We have used and intend to continue to use the net proceeds of the public offering primarily for general corporate purposes, including working capital and capital expenditures. The amounts and timing of these expenditures will vary depending on a number of factors, including the amount of cash generated or used by our operations, competitive and technological developments and the rate of growth, if any, of our business. We may also use a portion of the net proceeds to acquire businesses, services, products or technologies or invest in businesses that we believe will complement our current or future business. However, we have no specific plans, agreements or commitments and are not currently engaged in any negotiations for any material acquisition or investment. As a result, we will retain broad discretion in the allocation of the proceeds of the public offering. Pending the uses described above, we will invest the net proceeds of the public offering in cash, cash equivalents, money market funds or short-term interest-bearing, investment-grade securities to the extent consistent with applicable regulations. We cannot predict whether the proceeds will be invested to yield a favorable return.

Recent Sales of Unregistered Securities

      None.

Item 6.     Selected Consolidated Financial Data.

      The following selected consolidated balance sheets data as of December 31, 2001, 2000, 1999 and 1998 and the selected consolidated statements of operations data for each year in the five years ended December 31, 2001 have been derived from the audited consolidated financial statements. The selected balance sheet data as of December 31, 1997 has been derived from unaudited financial statements. The information set forth below is not necessarily indicative of results of future operations and should be read in conjunction with “Management’s Discussion and Analysis of Financial Conditions and Results of Operations” and the

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