SYNOPSYS INC - 10-K Annual Report

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UNITED STATES SECURITIES AND EXCHANGE COMMISSION
WASHINGTON, D.C. 20549

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FORM 10-K

[X] ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d)
OF THE SECURITIES EXCHANGE ACT OF 1934

FOR THE YEAR ENDED OCTOBER 31, 2001

OR

[ ] TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d)
OF THE SECURITIES EXCHANGE ACT OF 1934

COMMISSION FILE NUMBER 0-45138

SYNOPSYS, INC.
(Exact name of registrant as specified in its charter)

DELAWARE 56-1546236
(State or other jurisdiction of (I.R.S. Employer
incorporation or organization) Identification No.)

700 EAST MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA 94043
(Address of principal executive offices)

(650) 584-5000
(Registrant's telephone number, including area code)

SECURITIES REGISTERED PURSUANT TO SECTION 12(b) OF THE ACT: NONE

SECURITIES REGISTERED PURSUANT TO SECTION 12(g) OF THE ACT:
COMMON STOCK, $0.01 PAR VALUE

PREFERRED SHARE PURCHASE RIGHTS

Indicate by check mark whether the registrant (1) has filed all reports
required to be filed by Section 13 or 15(d) of the Securities Exchange Act of
1934 during the preceding 12 months (or for such shorter period that the
registrant was required to file such reports), and (2) has been subject to such
filing requirements for the past 90 days. [X] Yes No [ ]

Indicate by check mark if disclosure of delinquent filers pursuant to Item
405 of Regulation S-K is not contained herein, and will not be contained, to the
best of registrant's knowledge, in definitive proxy or information statements
incorporated by reference in Part III of this Form 10-K or any amendment to this
Form 10-K. [ ]

The aggregate market value of voting stock held by non-affiliates of the
registrant as of January 5, 2002, was approximately $2,522,354,670.

On January 5, 2002 approximately 60,543,491 shares of the registrant's
Common Stock, $0.01 par value, were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

Portions of the registrant's Notice of 2002 Annual Meeting and/Joint Proxy
Statement/Prospectus are incorporated by reference into Part III hereof.
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SYNOPSYS, INC.

ANNUAL REPORT ON FORM 10-K
YEAR ENDED OCTOBER 31, 2001

TABLE OF CONTENTS

1

PART I

This Form 10-K, including "Item 1. Business," includes forward-looking
statements within the meaning of Section 21E of the Securities Exchange Act of
1934. These statements include, but are not limited to, statements concerning:
the Company's business strategy; the Company's plans to expand its consulting
services business; the Company's expansion into the market for physical design
tools; the Company's intention regarding its system level design and
verification tools; the Company's intention regarding design reuse tools and
techniques; the Company's expectations regarding research and development, sales
and marketing, and general and administrative expenses; the Company's efforts to
enhance its existing products and develop or acquire new products; and the
Company's requirements for working capital. The Company's actual results could
differ materially from those projected in the forward-looking statements as a
result of risks and uncertainties that include, but are not limited to, those
discussed under the caption "Factors That May Affect Future Results" under
"Management's Discussion and Analysis of Financial Condition and Results of
Operations" included in Part II, Item 7 hereto, as well as factors discussed
elsewhere in this Form 10-K.

ITEM 1. BUSINESS

PENDING ACQUISITIONS

On July 2, 2001, the Company entered into an Agreement and Plan of Merger
with IKOS Systems, Inc. (IKOS), which manufactures hardware-assisted
verification systems. On December 3, 2001 the Company entered into an Agreement
and Plan of Merger with Avant! Corporation, which makes EDA software principally
serving the physical design portion of the market. The proposed mergers are
described under Item 7 below.

Except in limited respects, this report on Form 10-K discusses Synopsys'
business as of the end of fiscal 2001 and before giving effect to either
proposed merger.

INTRODUCTION

Synopsys, Inc. (Synopsys or the Company) is a leading supplier of
electronic design automation (EDA) software to the global electronics industry.
The Company's products are used by designers of integrated circuits (ICs),
including system-on-a-chip ICs, and the electronic products (such as computers,
cell phones, and internet routers) that use such ICs to automate significant
portions of their chip design process. ICs are distinguished by the speed at
which they run, their area, the amount of power they consume and the cost of
production. The Company's products offer its customers the opportunity to design
ICs that are optimized for speed, area, power consumption and production cost,
while reducing overall design time. The Company also provides consulting
services to assist customers with their IC designs, as well as training and
support services. Synopsys was incorporated in Delaware in 1987.

THE ROLE OF EDA IN THE ELECTRONICS INDUSTRY

Over the past three decades, technology advances in the semiconductor
industry have dramatically increased the size, speed and capacity of ICs:

- The number of transistors that can be placed on a chip has doubled
roughly every 18 months. A state-of-the-art IC may hold over 40 million
transistors. This is made possible in large part because the width of the
features on the chip is steadily shrinking. Mainstream IC designs today
are produced at a 0.18 micron process, with advanced chips being produced
at a 0.13 micron process. Over the next several years, the bulk of
production will shift to 0.13 micron or below.

- The speed at which chips operate has steadily increased. Microprocessors
operating at 2 gigahertz, a speed that was unheard of a few years ago,
are available today.

- Chips are also becoming more economical in their power consumption, which
is necessary to drive more and more powerful handheld devices.

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- Increasingly, functions that formerly were performed by multiple ICs
attached to a printed circuit board are being combined in a single chip,
referred to as a system-on-a-chip.

Combined, these changes have fostered the development of computers,
internet routers, wireless communications networks, hand-held personal digital
assistants, and many other goods and services with tremendous capabilities at
relatively low cost.

Competition and continuing innovation have shortened the life cycle of
electronic products, so time-to-market is crucial to the success of a product.
Time-to-market can in large part be determined by the time it takes to design
the chip that will run such product. EDA products play a critical role in
reducing time-to-market for new products by providing IC designers with tools
and techniques to (a) reduce the time and manual effort required to design,
analyze and verify individual ICs, (b) improve the performance and density of
complex IC designs and (c) enhance the reliability of the IC design and
manufacturing process.

THE DESIGN PROCESS

In simplified form, the design of an integrated circuit consists of five
basic steps:

System Design. First, a designer describes the functions that the chip is
to perform in a specialized high-level computer language. During this phase,
designers perform high level architectural design tradeoffs, to determine, for
example, which algorithms to use to implement the design, and what portions of
the design to implement in hardware and what portions in software. At the
completion of this phase, the designer produces a "register transfer level" or
"RTL" description of the chip. Most of this process is completed manually,
although there is a small but growing market for products that help automate
design and verification at the system level.

Logic Synthesis. After the designer is satisfied with the RTL code, a
logic synthesis program converts the RTL code into a logical diagram of the
chip. Related programs insert the circuitry that will be required to test the
chip after manufacture. A "gate level" (so called because it describes the
various logic blocks, or gates, required to implement the chip) data file, or
"net list", is produced. In a growing number of designs, the logic synthesis
phase is performed together with a portion of physical design. This combined
process, known as "physical synthesis", produces a file containing "placed
gates", which describes the logic blocks and includes information about where
they will be physically located, or "placed", on a chip. See discussion below
under "Current Issues Facing IC Designers". In a growing number of
system-on-a-chip ICs, in which multiple functions previously captured on
multiple chips are combined in a single chip, designers are increasingly
performing "chip planning", either before or in conjunction with logic
synthesis. In chip planning, the designer determines the location of the
functional "blocks" that will be captured on the system-on-a-chip and plans the
principal wire connections between the blocks. Logic synthesis is then
performed, more or less independently, on each block, before the blocks are
"stitched" back together.

High Level Verification. At this stage the designer uses simulation and
related programs to verify that the design, and for the individual blocks,
successfully perform the functions that the designer intended, by feeding an
exhaustive array of potential inputs into a specialized program, "simulating"
the functioning of the chip as designed, and checking to confirm that the
outputs match what was expected. Other techniques which use advanced
mathematical calculations rather than simulation are also used. The designer
also uses a timing analysis program to confirm that the chip as designed will
operate at the speed the designer intended.

Physical Design. If the designer is satisfied with the results of high
level verification, the transistors, and all of the wires connecting each one of
them, are mapped out in a series of transformations that gradually gets more and
more detailed. First, the location on the chip die of each block of the chip is
finalized, and the location of each transistor within each block is
determined -- a process known as "placement" -- then all of the connections
between the transistors are determined -- a process known as "routing". The
result is one or more data files that can be read by physical verification
programs (see below) or by the equipment used to manufacture the chip.

Physical Verification. Before sending the design data file to a chip
manufacturer for fabrication, a further verification step is undertaken. The
designer must confirm that the chip as placed and routed will
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operate at the speed anticipated during the logic design phase. The designer
also must check for unintended electrical effects that may arise as a
consequence of placing certain portions of the chip, or routing certain of its
"wires", too close together or in a bad position. Finally, the designer must
verify that the final design complies with all of the design rules set forth by
the party that will manufacture the chip.

The foregoing discussion has been greatly simplified. In the actual design
of a chip each of these steps has a number of different elements. The steps, or
the different elements within the steps, may be undertaken in a different order
or repeated one to multiple times. In any event, if at any stage of the process
the chip does not perform as intended, then the designer must go back one or
more steps to either redesign the RTL, redesign the logic, re-run the
verification or redo the physical design of the chip. Each iteration takes time,
and the more time the process takes, the more difficult it will be for the
designer to meet his or her time-to-market goals.

CURRENT ISSUES FACING IC DESIGNERS

As chip technology continues to advance, and particularly as the
state-of-the-art in chip design moves to 0.18 micron and below, Synopsys'
customers are facing a number of difficult design challenges:

Timing Closure. Ensuring that a chip will run at the desired speed becomes
substantially more difficult as transistor sizes move to 0.18 micron and below.
At larger transistor feature sizes, IC designers could use standard estimates of
chip timing during the logic design phase, and be confident that the timing
characteristics would be preserved through the physical design phase. At 0.18
micron and below, these estimates become more and more unreliable. To address
this problem, customers will increasingly need products (referred to in the EDA
industry as "physical synthesis" products) that integrate logic design and
physical design. Synopsys' physical synthesis solution takes physical design
information into account during logic design, and produces a file containing
"placed gates". Physical synthesis provides more accurate timing estimates at
the logic design phase, greatly improving the correlation between original
timing estimates after logic design and timing results after physical design.

Signal Integrity Closure. Signal integrity refers to a variety of
electrical effects that can cause circuits to behave in undesirable ways. The
electrical characteristics of ICs of 0.13 micron and below cause previously
insignificant effects to become problematic. These effects include cross-talk,
voltage drop, and electro-migration. Cross-talk, in particular, is becoming a
major problem for advanced designs today. In order to address signal integrity
problems designers need products that help them analyze, prevent and repair
errors caused by signal integrity issues. Synopsys has added cross-talk analysis
to its PrimeTime timing analysis product to aid designers in detecting
cross-talk-induced timing violations. Synopsys' physical synthesis tools include
analysis, prevention and repair features to achieve signal integrity closure
more quickly and reliably.

Verification. Verification is the process of ensuring, at various stages
of the design process, that a chip will perform as intended. As the number of
transistors on a chip grows, the verification problem grows geometrically. In
fact, with today's chips, verification often takes up the single largest
proportion of the overall design process. Verification products must offer
customers a combination of speed, accuracy and the ability to focus on the
portions of the chip most likely to cause problems.

Designer Productivity. Historically, finding, hiring and retaining
qualified design engineers has been one of the most difficult problems that our
customers face. Without enough designers it is difficult for a company to meet
ambitious development schedules, and to get its products to market in a timely
manner. Although hiring qualified designers has become less difficult in the
current economic environment, the increase in IC complexity and time to market
pressures have resulted in a continuing emphasis on designer productivity. For
EDA companies, this creates opportunities both in providing full-featured,
integrated design flows, that reduce the number of iterations required during
the design process, and in offering pre-designed, pre-verified design "building
blocks" that can be re-used in multiple designs.

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SYNOPSYS OVERVIEW

Synopsys provides products and services that help customers meet the
challenges of designing leading edge ICs and the products that incorporate them.

Synopsys offers a comprehensive suite of logic synthesis and related
products that allow an IC designer to describe chip behavior in a high-level
language and convert that description into a map of the chip's logic blocks,
including circuits that facilitate testing of the chip before it is fabricated.
Synopsys has been working on extending its design tools product line to include
several products that integrate logic design and physical design.

Synopsys' high level and physical verification products are used by IC
designers in several stages of the IC design process to ensure that the
resulting IC performs the function that the designer intended. Synopsys'
simulation products permit IC designers to simulate their designs and to explore
tradeoffs between incorporating functionality in hardware or software. Synopsys
also offers a suite of products that help designers focus on the most
problematic portions of their chips. And to help customers analyze other aspects
of chip performance, Synopsys offers an extensive line of software tools to
analyze power, timing and reliability concerns in an IC design at the RTL, gate
and transistor levels.

Synopsys provides the broadest array of reusable design building blocks of
any company in the EDA and intellectual property (IP) industry. The Company's IP
products also include software and hardware models, which are used to test an IC
design within the context of the system in which the IC will eventually be used.

Synopsys also offers a full range of professional services to help
customers improve their internal design methodologies, as well as design
services ranging from specialized assistance to turnkey design.

Synopsys markets its products on a worldwide basis and offers comprehensive
customer service, education, consulting, and support as integral components of
its product offerings. Products are marketed primarily through its direct sales
force. Synopsys has licensed its products to most of the world's leading
semiconductor, computer, communications and electronics companies.

STRATEGY

Synopsys' strategy is to develop and offer to its customers a broad array
of tools and services required to enable design of complex ICs, especially
system-on-a-chip ICs. The Company is seeking to build and enhance products that
help customers address the most pressing problems of IC design at 0.18 micron
and below: timing closure, signal integrity and closure, verification, and
designer productivity. First, building from its historical base of strength in
high level design, Synopsys plans to help customers address the timing closure
problem by continuing its expansion into the market for physical synthesis
products -- products that integrate logical and physical design. Second,
Synopsys will seek to address signal integrity issues by developing products
that help designers analyze, prevent and fix signal integrity problems at
different levels of the design process. Third, Synopsys will seek to help
customers address their verification needs by building a comprehensive offering
of verification products around its current position in simulation, test and
timing analysis. Fourth, Synopsys intends to help customers address the designer
shortage by expanding its inventory of reusable design building blocks, which
will allow customers to focus their own design teams on areas of competitive
differentiation, and by offering professional services to supplement customers'
own design teams.

PRODUCTS

Synopsys products and services are focused on the principal needs of IP and
systems designers, and can be divided into five categories -- IC Implementation,
Verification and Test, IP and Systems Level Design, Transistor Level Design and
Professional Services. The products included in these categories are discussed
below. Financial information regarding these products is included under Item
7 -- Management's Discussion and Analysis of Financial Condition and Results of
Operation -- "Results of Operation -- Revenue -- Product Groups".

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IC IMPLEMENTATION PRODUCTS

Synopsys' IC Implementation products include the Company's basic logic
synthesis and related products, and the Company's new physical synthesis
products.

During fiscal 2001, IC Implementation products accounted for 40% of the
Company's revenues.

Logic synthesis is the process by which a high-level description of desired
chip functions is mapped into a connected collection of logic gates and other
circuit elements that perform the desired functions. Design Compiler(TM) is the
market-leading logic synthesis tool and is used by a broad range of companies
engaged in the design of ICs to optimize their designs for performance and area.
Design Compiler was introduced in 1988 and has been updated regularly since
then. The Company's Design Compiler product family also includes Power Compiler
and Module Compiler. Power Compiler provides "push-button" power optimization
and early analysis for the design of low power circuits, which are key for the
design of hand-held devices. Module Compiler is used in the design of complex
datapaths.

In fiscal 2001, Synopsys released Design Compiler 2001 as the latest
generation in the Design Compiler family. Design Compiler 2001 features
significant enhancements, including improved optimization algorithms, run-times
and capacity. Over time, Synopsys expects that a significant portion of the
existing Design Compiler license base will be upgraded to Physical Compiler
(discussed below), although Design Compiler will continue to be an important
element in designers overall suite of design tools, especially for performing
logic synthesis on non-timing-critical portions of a design.

Physical synthesis unites logic synthesis, placement and, in the future,
routing and links them together with common timing. When used together, the
physical synthesis suite of products provides customers with an integrated
design flow from register transfer level through placement and routing, and
addresses the critical timing problems encountered in designing advanced ICs and
systems-on-a-chip.

Physical Compiler, released by the Company in 2000, unifies synthesis and
placement in a single product in order to greatly improve designers' ability to
achieve timing closure. As of October 2001, Physical Compiler had been licensed
to over 120 customers and more than 350 IC designs had been completed using the
product. During fiscal 2001, the Company received approximately $100 million in
orders for Physical Compiler.

The physical synthesis suite of products also includes Chip Architect,
FlexRoute, ClockTree Compiler, and Route Compiler. Chip Architect is a
hierarchical design planner, which takes into account physical phenomena and is
used at various stages of the system-on-a-chip design process to perform
chip-level estimation, floor-planning, timing analysis and placement. FlexRoute
is a high-capacity, object-based, top-level router, which is used to route the
longest, most-difficult-to-route connections between functional blocks on a
system-on-a-chip. During fiscal 2001, the Company announced Route Compiler and
Clock Tree Compiler and began working with four target customers to enhance the
product for broader release. Commercial release of these products is expected in
the first half of calendar 2002. ClockTree Compiler is a clock tree synthesis
option to Physical Compiler that integrates design and clock tree synthesis into
one tool. Route Compiler is a standard cell router integrated into Physical
Compiler that completes detailed routing.

The Company's IC Implementation products also include logic synthesis
products for field programmable gate arrays (FPGAs) and complex programmable
logic devices (CPLDs). With the advent of high-density chips (.25 micron and
below), FPGAs have become fast and large enough to handle a substantial fraction
of projects that previously required mask-programmed application specific
integrated circuits (ASICs). Furthermore, FPGAs' unique ability to deliver very
quick time-to-market make them attractive in today's business environment. An
enhanced version of FPGA Compiler II(TM) offering enhanced synthesis for Xilinx
and Altera FPGA devices was released in fiscal 2001.

VERIFICATION AND TEST PRODUCTS

The Company's Verification and Test products consist of a group of tools,
including simulation, test automation and timing verification products, to
enable IC designers to quickly and reliably verify the behavior

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of a design before it is committed to the expensive and time-consuming process
of IC fabrication, and to assist in the testing of the chip after manufacturing.

During fiscal 2001, Verification and Test products accounted for 29% of the
Company's revenues.

Simulation and related products. Simulation software "exercises" an IC
design by running it through a series of tests and comparing the actual outputs
from the design with the expected output. As such, simulation products are the
key products for functional verification. The goal of simulation is to make sure
that the functionality of the design meets the original specifications of the
chip. Synopsys offers two products for high-level simulation: VCS(TM), for
designs written in Verilog (one of the two principal languages) and
Scirocco(TM), for designs written in VHDL (the other principal language).
Simulation products are distinguished principally by their runtime and
capacity -- i.e., how fast they can fully simulate a proposed design and how
large a design they can handle. The Company is focused on providing the
industry's fastest and highest-capacity simulation technology and believes that
both VCS and Scirocco are industry leaders in performance and capacity. VCS is
supported by all major semiconductor manufacturers and many third-party EDA
software providers.

In addition to focusing on building the fastest simulator, Synopsys is
focused on developing a suite of products that help simulation products work
"smarter". The Company estimates that more time is spent in writing verification
"testbenches" than in creating the design description. Testbenches, which create
stimuli for chips and check the results, are used in conjunction with simulation
tools to verify that a design functions as expected. Synopsys provides software
that helps generate and manage testbenches as well as evaluate the effectiveness
of the simulation process. VERA(R) is a tool that automates the design of
testbenches, thereby offering the IC designer significant reductions in overall
design and verification time. VERA provides a high-level language designed
specifically for verifying complex designs. VERA is integrated with the
Company's other simulation products.

Test Automation. In order to meet today's stringent quality requirements,
chips must pass through rigorous testing after manufacturing. Synopsys'
design-for-test (DFT) tools offer a complete DFT solution. Synopsys' DFT
Compiler, the industry-standard 1-pass test synthesis product, inserts all
functional and test logic required to enable efficient, high-coverage testing of
the chip after manufacturing, while complying with the customer's design rules
and constraints (timing, area, power, etc.). DFT Compiler works seamlessly with
Design Compiler and Physical Compiler, with the added benefit, in the case of
Physical Compiler, of placement-driven optimization of test logic. DFT Compiler
was awarded the 2001 "Best in Test" Award from Test & Measurement World, an
industry journal. The award is presented annually to honor important and
innovative products in the electronics test and measurement industry.

Automatic test pattern generation (ATPG) is the other component of
Synopsys' complete DFT solution. TetraMAX(TM) ATPG, the Company's ATPG product
is optimized for ease-of-use, capacity, speed, coverage and vector compaction.
TetraMAX ATPG works in concert with DFT Compiler to enable total automation of
the DFT flow. Synopsys test methodology also includes software to facilitate the
failure diagnosis of chips after manufacturing test, expediting the
time-consuming and expensive post-fabrication activities required to determine
the cause of manufacturing defects.

Static Timing Analysis. Synopsys provides a complete tool suite to help
designers perform static timing analysis at the gate and transistor levels and
analyze signal integrity issues such as cross-talk. Synopsys' gate level
analysis tool is called PrimeTime(R). PrimeTime is a full-chip, gate-level
static timing analysis tool targeted for complex multimillion gate designs,
which is used by designers to verify, at various stages of the design process,
the speed at which a design will operate when it is fabricated. PrimeTime's
analysis of a design's speed is accepted as a "sign off" tool by virtually all
major semiconductor manufacturers, which means that they accept its analysis as
determinative. (Synopsys transistor-level timing analysis products are described
below under "Transistor Level Design"). In fiscal 2001, Synopsys extended
PrimeTime's capabilities with the introduction of PrimeTime-SI, which analyzes
the effect of cross-talk on timing, an increasingly important issue at chip
geometries below 0.18 micron.

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Formal Verification -- Equivalence Checking. Formal verification is a
method for comparing two versions of a design to determine if they are
equivalent. Usually an RTL version of the design is validated using simulation
and other dynamic verification tools, establishing it as the golden version.
Subsequent versions (i.e., after each step of the design process) are then
compared to the golden version, using mathematical algorithms, to determine if
they are functionally equivalent. The use of formal verification greatly reduces
the need to perform simulation, which is substantially more time-consuming, at
each stage of the design process, thus potentially saving a significant amount
of time in the overall design process. Synopsys' formal verification product is
Formality(R). Formality was one of the industry's first commercial equivalency
checkers to employ a multi-solver architecture, which enables the verification
of complex multimillion-gate system-on-a-chip designs in days or minutes.

INTELLECTUAL PROPERTY (IP) AND SYSTEMS LEVEL DESIGN

The Company's IP and Systems Level Design products include our DesignWare
IP library and systems design and verification products.

During fiscal 2001, IP and Systems Level Design products accounted for 12%
of the Company's revenues.

Intellectual Property Products. As IC designs continue to grow in size,
reusing design blocks is becoming a more important method for reducing overall
design cycle time. By reusing portions of a design, and particularly those that
implement basic or standardized functions, a company can let its IC design team
focus on designing the chip features that will give its product a competitive
advantage. It can also reduce its verification risk by ensuring that these
portions of the chip are of high quality. Enabling reuse of intellectual
property (IP) requires a significant methodology shift from traditional IC
design. In the past, designs were intimately tied to a particular semiconductor
process technology or design methodology, making reuse of design blocks from one
chip design to the next, both difficult and costly.

Synopsys' DesignWare(R) product provides IC designers with a single library
of pre-designed and pre-verified synthesizable IP cores as well as over 18,500
verification IP models. The synthesizable IP cores range in complexity from
simple adders and multipliers to PCI-X and USB2.0 cones. The verification IP
models range in complexity from standard 74XX TTL parts to models of complex bus
interface protocols. These models support all major EDA simulation environments
and a wide range of EDA platforms, giving designers access to a broad range of
models to assist them with verification of their designs.

To meet the new challenges of SoC designs, in 2001 Synopsys announced its
Star IP program in which DesignWare users can gain access to popular
microprocessors from MIPS Technologies, Infineon Technologies, NEC and other
providers. In addition, during 2002, the Company expects to add a complete AMBA
On-Chip-Bus to DesignWare.

The Company's IP and Systems Level Design products also include a full
range of hardware modeling solutions. ModelSource(TM) 3000 series is a family of
hardware modeling systems for ASIC and board level design which provide a
flexible means for designers to model complex devices. ModelSource 3000 systems
use the actual integrated circuit to model its own behavior in a larger system.

Systems Design and Verification Products. Currently, automated design
generally begins at the register transfer level, with logic synthesis. The goal
of "system-level" products is to permit designers to design and verify their
products at a level of abstraction above RTL. Synopsys' systems products consist
of the CoCentric(TM) family of tools and methodologies for concurrent design,
validation, refinement and implementation of an electronic system.

The CoCentric family of products is based on "SystemC,(TM)" a standard
language developed by Synopsys and now available under an open source license.
SystemC enables designers to create, validate and share system level models of a
complex IC or system incorporating the chip, and therefore can be used to
explore and verify design alternatives at an early stage of the design process.
EDA and IP vendors have complete access to the SystemC modeling platform
enabling them to build interoperable tools and IP models. SystemC is managed by
the Open SystemC Initiative (OSCI), a not-for-profit organization which includes
representation from the systems, semiconductor, IP, embedded software and EDA
industries. The OSCI Board of
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Directors is composed of representatives from ARM Ltd., Cadence Design Systems,
CoWare, Fujitsu Microelectronics, Mentor Graphics, Motorola, NEC, and Synopsys.

The Company offers two principal products based on SystemC. CoCentric
System Studio is a system-level design environment for the rapid creation of
executable system specifications that can be verified and implemented as
hardware and software functions. System Studio enables designers to use
hierarchical graphical and language modeling to capture system complexity in a
unified environment based on C, C++ and SystemC. System Studio supports
verification of hardware and software design refinements through concurrent
execution of C-based specifications, popular hardware simulators, and a variety
of processor models. Synopsys is in the process of migrating customers of its
COSSAP(R) design system to CoCentric System Studio.

CoCentric SystemC Compiler is a synthesis tool that allows designers to
implement complex circuits from SystemC, enabling design to progress from an
initial C/C++ executable specification into a database readable by Synopsys'
Design Compiler. Eliminating the need to remodel in Verilog or VHDL, SystemC
Compiler accelerates the design cycle by closing the gap between system
designers and hardware designers. SystemC Compiler allows designers to rapidly
create alternative implementations of a design at high abstraction, enabling
them to spend time productively evaluating tradeoffs in performance, size and
power consumption before committing to a particular implementation.

In January 2001, the Company sold its business consisting of silicon
libraries of logic functions to Artisan Components, Inc.

TRANSISTOR LEVEL DESIGN PRODUCTS

Synopsys' transistor level design products include a range of products in
the areas of timing analysis and verification; power management; circuit
simulation and IP verification. These products, which are used after the
completion of physical design, help customers analyze the increasingly important
electrical effects resulting from designing at 0.18 micron and below, and to
locate implementation errors that can be costly and time-consuming to correct
during or after production. As the logic and physical design phases of IC
Implementation grow more and more integrated, the Company is also integrating
many of its transistor level design products with its high level verification
products, particularly in the areas of simulation, timing, and power analysis.

During fiscal 2001, Transistor Level Design products accounted for 7% of
the Company's revenues.

Static Timing Analysis. As part of its overall approach to timing analysis
and verification, Synopsys offers PathMill(R), PathMill Plus and AMPS(R).
PathMill is a transistor-level static timing analysis tool for custom
microprocessor and DSP designs. PathMill's analysis provides SPICE-level
accuracy with 1000x performance improvement over traditional SPICE. PathMill
Plus extends PathMill to offer advanced modeling, model merging and verification
to speed characterization of custom IP blocks. The combination of PrimeTime and
PathMill offers full-chip static timing analysis that covers transistor- to
gate-level designs. These tools are integrated with Arcadia, Synopsys'
resistance and capacitance (RC) extraction tool.

Circuit Simulation. In fiscal 2001, Synopsys introduced NanoSim, an
advanced circuit simulator for memory and mixed-signal verification, which
combines simulation technologies from TimeMill and PowerMill to deliver circuit
simulation, timing, and power analysis in a single tool. NanoSim offers a tight
integration with Synopsys' VCS simulator to deliver high-speed high-capacity
verification of complex ICs. NanoSim and VCS together address verification
challenges at RTL, gate- and transistor-levels, and enable mixed-signal
multi-level verification of complex ICs. NanoSim further enables this flow by
supporting Verilog-A, the industry-standard analog behavioral modeling language.
TimeMill(R) and PowerMill(R) continue to provide high-accuracy, high-speed and
high- capacity circuit simulation technology.

Power Management. Synopsys delivers a complete solution to help designers
manage and verify power consumption at different levels of the design process.
These products include: Power Compiler (described under IC Implementation
category), PrimePower, PowerArc, NanoSim and RailMill. PrimePower is a dynamic,
full-chip power analysis tool for complex multimillion-gate ASICs. PrimePower
allows users to
9

quickly and efficiently verify that their IC designs meet power budgets and
specifications, select the proper packaging, determine cooling requirements and
estimate the battery life for portable applications. As a foundation for
Synopsys' power solution, PowerArc delivers automatic cell library power
characterization, making it easy for library providers and ASIC and silicon
vendors to automatically produce power libraries with SPICE-level accuracy.

SYNOPSYS PROFESSIONAL SERVICES BUSINESS UNIT

Synopsys Professional Services provides a comprehensive portfolio of
consulting services covering all critical phases of the system-on-a-chip
development process, as well as systems development in wireless and broadband
applications. Customers are offered a variety of engagement models ranging from
project assistance -- which helps a customer design, verify and/or test its
chips and improve its design process -- to full turn-key development.

During fiscal 2001, the Synopsys Professional Services business unit
accounted for 12% of the Company's revenues.

ORGANIZATION

Synopsys is currently organized into four product development groups --
Physical Synthesis, Verification Technology, Intellectual Property and Systems,
and Nanometer Analysis and Test -- and a services group -- Synopsys Professional
Services. The Physical Synthesis business unit principally develops and manages
our IC Implementation products. The Verification Technology business unit
develops and manages the simulation products in our Verification and Test
product portfolio. The Intellectual Property and Systems business unit develops
and manages all of the product in the IP and Systems Level Design product
category. The Nanometer Analysis and Test business unit develops and manages the
timing analysis, power and test products in the Verification and Test product
category, and the products in the Transistor Level Design category. In addition
to these product and services groups, Synopsys maintains a World Wide Sales
group, a World Wide Application Services group, a Finance group, a Human
Resources group, and a Technology and Information Systems group.

CUSTOMER SERVICE AND SUPPORT

Synopsys devotes substantial resources to providing customers with
technical support, customer education, and consulting services. The Company
believes that a high level of customer service and support is critical to the
adoption and successful utilization of high-level design automation methodology.
In fiscal 2001, service revenue as a percentage of total revenue increased to
50% as compared to 43% in fiscal 2000.

TECHNICAL SUPPORT

Technical support for the Company's products is provided through both
field- and corporate-based technical application engineering groups. Synopsys
provides customers with software updates and a formal problem identification and
resolution process through the Synopsys Technical Support Center. Synopsys'
central entry point for all customer inquiries is SolvNet(R), a direct-access
service available worldwide, 24 hours per day, through electronic mail and the
World Wide Web that lets customers quickly seek answers to design questions or
more insight into design problems. SolvNet combines Synopsys' complete design
knowledge database with sophisticated information retrieval technology. Updated
daily, it includes documentation, design tips, and answers to user questions.

CUSTOMER EDUCATION SERVICES

Synopsys offers workshops on many aspects of high-level design languages,
high-level design, simulation, synthesis, physical design, system design and
test. Regularly scheduled workshops are offered in Mountain View, California;
Austin, Texas; Burlington, Massachusetts; Reading, England; Rungis, France;
Munich, Germany; Tokyo and Osaka, Japan; Seoul, Korea and other locations.
On-site workshops are worldwide at

10

customers' facilities or other locations. Over 11,000 design engineers attended
Synopsys workshops during fiscal 2001.

PRODUCT WARRANTIES

Synopsys generally warrants its products to be free from defects in media
and to substantially conform to material specifications for a period of 90 days.
Synopsys has not experienced significant returns to date.

SUPPORT FOR INDUSTRY STANDARDS

Synopsys actively creates and supports standards it believes will help its
customers increase productivity and solve design problems, including key
interfaces and modeling languages that promote system-on-a-chip design and
facilitate interoperability of tools from different vendors. Standards in the
EDA industry can be established by formal accredited committees, by licensing
made available to all, or through open source licensing.

Synopsys' products support many formal standards, including the two most
commonly used hardware description languages, VHDL and Verilog HDL, and numerous
industry standard data formats for the exchange of data between Synopsys' tools
and other EDA products.

Synopsys is a board member and/or participant in the following major EDA
standards organizations: Accellera, a not-for-profit formal standards
organization that drives language-based standards for systems, semiconductor,
and design tools companies; the interoperability committee of the EDA
Consortium, which helps promote interoperability among EDA products from
different vendors; and the Virtual Socket Interface Alliance (VSIA), an industry
group formed to promote standards that facilitate the integration and reuse of
functional blocks of intellectual property.

Synopsys' TAP-in program provides interface standards to all companies
through an open source licensing model. Interface formats and reference
implementations, such as parsers and screeners, are available to everyone at no
cost through the Internet. Synopsys manages changes and enhancements that come
from the community of licensees. The open source standards and reference
implementations are used by Synopsys, other EDA companies and EDA customers to
interface tools with each other to produce flexible design flows. The standards
provided by Synopsys as open sources include Liberty for library modeling, SDC
for design constraints, and OpenVera for hardware verification.

SystemC, an open industry standard language, is discussed above under
"Intellectual Property and Systems Products."

Synopsys' products are written mainly in the C and C++ languages and
utilize industry standards for graphical user interfaces. Synopsys' software
runs under UNIX operating systems, such as Solaris and HP-UX, and most products
also run on the open source Linux operating system. Synopsys' products are
offered on the most widely used hardware platforms, including those from Sun
Microsystems, Hewlett-Packard, IBM, and Intel microprocessor-based PCs.

SALES, DISTRIBUTION AND BACKLOG

Synopsys markets its products and services primarily through its direct
sales and application service forces in the United States and principal
international markets. Synopsys employs highly skilled engineers and technically
proficient sales persons in order to understand our customer's needs and to
explain and demonstrate the value of Synopsys' products.

For fiscal 2001, 2000 and 1999, international sales represented 37%, 42%
and 34%, respectively, of Synopsys' total revenue. Additional information
relating to domestic and foreign operations is contained in Note 8 of Notes to
Synopsys' Consolidated Financial Statements.

The Company has sales/support centers throughout the United States, in
addition to its Mountain View, California headquarters. Internationally, the
Company has sales/support offices in Canada, Denmark, Finland, France, Germany,
Hong Kong, India, Israel, Italy, Japan, Korea, the People's Republic of China,
Singapore,
11

Sweden, Taiwan and the United Kingdom, including international headquarters
offices in Ireland. On a very limited basis, the Company also utilizes
manufacturer's representatives and distributors. The Company's offices are
further described under "Item 2 -- Properties."

Synopsys' backlog on December 1, 2001 was approximately $802.7 million,
compared to approximately $462.8 million on December 1, 2000.

This backlog consists of orders for system and software products sold under
perpetual and time-based licenses with customer requested ship dates within
three months which have not been shipped, orders for customer training and
consulting services which are expected to be completed within one year, and
subscription services, maintenance and support with contract periods extending
up to fifteen months. In the case of a Technology Subscription License (TSL),
including a multiyear TSL, backlog includes the full amount of the committed
non-cancelable order, less any amount of revenue that has been recognized on
such TSL.

The Company has not historically experienced significant cancellations of
orders. Customers frequently reschedule or revise the requested ship dates of
orders, however, which can have the effect of deferring recognition of revenue
for these orders beyond the expected time period.

RESEARCH AND DEVELOPMENT

The Company's future performance depends in large part on its ability to
maintain and enhance its current product lines, develop new products, maintain
technological competitiveness and meet an expanding range of customer
requirements. In addition to research and development conducted within each
business unit, the Company maintains an advanced research group that is
responsible for exploring new directions and applications of its core
technologies, migrating new technologies into the existing product lines and
maintaining strong research relationships outside the Company within both
industry and academia.

During fiscal 2001, 2000 and 1999, research and development expenses, net
of capitalized software development costs, were $189.8 million, $189.3 million
and $167.1 million, respectively. Synopsys capitalized software development
costs of approximately $1.0 million, $1.0 million and $0.9 million in fiscal
2001, 2000 and 1999, respectively. The Company anticipates that it will continue
to commit substantial resources to research and development in the future.

MANUFACTURING

Synopsys' manufacturing operations consist of assembling, testing,
packaging and shipping its system and software products and documentation needed
to fulfill each order. Manufacturing is currently performed in Synopsys'
Mountain View, California and Dublin, Ireland facilities. Outside vendors
provide CD-ROM replication, printing of documentation and manufacturing of
packaging materials. Synopsys typically ships its software products within 10
days of acceptance of customer purchase orders and execution of software license
agreements unless the customer has requested otherwise. Upon customer request,
Synopsys delivers its software products through electronic means rather than
shipping disks. This method of delivery is becoming increasingly common for
customers worldwide.

Synopsys employees manufacture and test the hardware modeling system
products, with most sub-assembly performed by outside vendors. For its hardware
modeling products, Synopsys buys components and assemblies in anticipation of
orders and configures units to match orders, typically shipping within one to
ten weeks of order acceptance, unless the customer has requested otherwise.

COMPETITION

The EDA industry is highly competitive. We compete against other EDA
vendors, and with customers' internally developed design tools and internal
design capabilities for a share of the overall EDA budgets of our potential
customers. In general, competition is based on product quality and features,
post-sale support, price and, as discussed below, the ability to offer a
complete design flow. Our competitors include companies that offer a broad range
of products and services, such as Cadence Design Systems, Inc., Avant! and
Mentor
12

Graphics Corporation, as well as companies, including numerous start-up
companies, that offer products focused on a discrete phase of the integrated
circuit design process. In certain situations, Synopsys' competitors have been
offering aggressive discounts on certain of their products, in particular
simulation and synthesis products. As a result, average prices for these
products may fall. In order to compete successfully, we must continue to enhance
our products and bring to market new products that address the needs of our
customers. We also will have to expand our consulting services business. The
failure to enhance existing products, develop and/or acquire new products or
expand our ability to offer consulting services could have a material adverse
effect on our business, financial condition and results of operations.

Technology advances and customer requirements continue to fuel a change in
the nature of competition among EDA vendors. Increasingly, EDA companies compete
on the basis of "design flows" involving integrated logic and physical design
products rather than on the basis of individual "point" tools performing a
discrete phase of the design process. A number of companies, including, Cadence,
Avant!, Magma Design, Synplicity and Monterey Design, are developing or selling
products that link logic and physical design. The need to offer such design flow
synthesis products will become increasingly important, as ICs grow more complex.
In fiscal 2001, we announced new products that would extend our design flow
through physical design, and begin working with target customers to prepare such
products for broader release. If we are unsuccessful in developing a complete
design flow on a timely basis or in convincing customers to adopt our integrated
logical and physical design products and methodology, our competitive position
could be significantly weakened.

PRODUCT SALES AND LICENSING AGREEMENTS

Synopsys typically licenses its software to customers under non-exclusive
license agreements that transfer title to the media only and that restrict use
of the software to specified purposes within specified geographical areas. The
Company currently licenses the majority of its software as a network license
that allows a number of individual users to access the software on a defined
network. License fees are dependent on the type of license, product mix and
number of copies of each product licensed.

Synopsys currently offers its software products under either a perpetual
license or a short-term ratable license. Under a perpetual license a customer
pays a one-time license fee for the right to use the software. The vast majority
of customers buying perpetual licenses also purchase annual software support
services for perpetual licenses, under which they receive minor enhancements to
the products developed during the year, bug fixes and technical assistance. A
ratable license, and the various forms of time-based licenses that the Company
has offered before introducing ratable licenses, operates like a rental of
software which typically includes software support services. A customer pays a
fee for license and support over a fixed period of time, and at the end of the
time period the license expires unless the customer pays for a renewal. Ratable
licenses are offered with a range of terms; the average length is approximately
3.0 to 3.5 years. See "Management's Discussion and Analysis of Financial
Condition and Results of Operations -- Results of Operations -- Revenue".

Over the past several years, orders for time-based licenses (now ratable
licenses) have increased significantly as a percentage of total product orders.
During fiscal 2001, orders for time-based licenses, including ratable licenses,
accounted for 86% of total product orders compared to 74% in fiscal 2000 and 64%
in fiscal 1999.

During fiscal 2002 Synopsys expects that orders for ratable licenses will
account for approximately 75% to 85% of total product orders and orders for
perpetual licenses approximately 15% to 25% of total product orders.

Synopsys offers its hardware modeler products for sale or lease.

PROPRIETARY RIGHTS

The Company primarily relies upon a combination of copyright, patent,
trademark and trade secret laws and license and nondisclosure agreements to
establish and protect proprietary rights in its products. The source code for
Synopsys' products is protected both as a trade secret and as an unpublished
copyrighted work.

13

However, it may be possible for third parties to develop similar technology
independently. In addition, effective copyright and trade secret protection may
be unavailable or limited in certain foreign countries. The Company currently
holds U.S. and foreign patents on some of the technologies included in its
products and will continue to pursue additional patents in the future.

Although the Company believes that its products, trademarks and other
proprietary rights do not infringe on the proprietary rights of third parties,
there can be no assurance that infringement claims will not be asserted against
the Company in the future or that any such claims will not require the Company
to enter into royalty arrangements or result in costly and time-consuming
litigation.

EMPLOYEES

As of November 3, 2001, Synopsys had a total of 3,223 employees, of whom
2,351 were based in North America and 872 were based internationally. Synopsys'
future financial results depend, in part, upon the continued service of its key
technical and senior management personnel and its continuing ability to attract
and retain highly qualified technical and managerial personnel. Competition for
such personnel is intense. Our success is dependent on technical and other
contributions of key employees. We participate in a dynamic industry, with
significant start-up activity, and our headquarters is in Silicon Valley, where
skilled technical, sales and management employees are in high demand. There are
a limited number of qualified EDA and IC design engineers, and the competition
for such individuals is intense. Experience at Synopsys is highly valued in the
EDA industry and the general electronics industry, and our employees are
recruited aggressively by our competitors and by start-up companies in many
industries. In the past, we have experienced, and may continue to experience,
significant employee turnover. There can be no assurance that Synopsys can
retain its key managerial and technical employees or that it can attract,
assimilate or retain other highly qualified technical and managerial personnel
in the future. None of Synopsys' employees is represented by a labor union.
Synopsys has not experienced any work stoppages and considers its relations with
its employees to be good.

ITEM 2. PROPERTIES

Synopsys' principal offices are located in four adjacent buildings in
Mountain View, California, which together provide approximately 400,000 square
feet of available space. This space is leased through February 2015. Within one
half mile of these buildings, in Sunnyvale, California, Synopsys occupies
approximately 200,000 square feet of space in two adjacent buildings, which are
under lease through 2007, and approximately 85,000 square feet of space in a
third building, which is under lease until April 2007.

The Company currently leases approximately 45,000 square feet in Dublin,
Ireland for its international headquarters and for research and development
purposes. This space is leased through April 2025.

The Company leases approximately 93,000 square feet of space in Beaverton,
Oregon for administrative, marketing, research and development and support
activities. This facility is leased through March 2002, and will be replaced by
the newly constructed site in Hillsborough, Oregon.

In addition, the Company leases approximately 82,000 square feet of space
in Marlboro, Massachusetts for sales and support, research and development and
customer education activities. This facility is leased through March 2009.

The Company currently leases 25 other sales offices throughout the United
States. Synopsys currently leases international sales and service offices in
Canada, Finland, France, Germany, Hong Kong, India, Israel, Italy, Japan, Korea,
the People's Republic of China, Singapore, Sweden, Taiwan, and the United
Kingdom. The Company also leases research and development facilities in France,
Germany and India.

Synopsys owns a fourth building in Sunnyvale, with approximately 120,000
square feet, which is leased to a third party through May 2003. Synopsys also
owns thirty-four acres of undeveloped land in San Jose, California and 13 acres
of undeveloped land in Marlboro, Massachusetts. Additionally, Synopsys owns
forty-four acres of land in Hillsborough, Oregon on which two buildings,
totaling 236,000 square feet, are being constructed. In February 2002, this
facility will replace the leased site in Beaverton.
14

ITEM 3. LEGAL PROCEEDINGS

On December 6, 2001, Mentor Graphics and its subsidiary Fresno Corporation
filed a lawsuit in the Court of Chancery of the State of Delaware (C.A. No.
19299) against IKOS, the members of IKOS' board of directors, Synopsys and
Synopsys' subsidiary Oak Merger Corporation ("Oak"). The lawsuit claims that
certain provisions of the Synopsys -- IKOS Merger Agreement ("Merger
Agreement"), including the termination fee and no-shop provisions and certain
restrictive covenants relating to the interim operations of IKOS, were entered
into in breach of the IKOS directors' fiduciary duties, and that Synopsys and
Oak aided and abetted those breaches. The lawsuit seeks, among other relief,
injunctive and declaratory relief, including an order enjoining the enforcement
of the no-shop and termination fee provisions of the Merger Agreement, and
unspecified damages. On January 2, 2002, Synopsys and Oak filed a motion to
dismiss Mentor Graphics' complaint. No date has been set for trial in this
matter but the parties have begun to engage in discovery.

On December 10, 2001, Ernest Hack, an alleged stockholder of IKOS, filed an
alleged class action lawsuit in the Court of Chancery of the State of Delaware
(C.A. No. 19305) against IKOS, the IKOS directors and Synopsys. While not
identified as such in the caption of the complaint, the body of the complaint
also describes Mentor Graphics as a defendant. This lawsuit alleges that the
members of IKOS' board failed to properly consider and act upon Mentor Graphics'
offer to acquire IKOS. The lawsuit also alleges that IKOS failed to solicit
offers before entering the Merger Agreement. The lawsuit alleges that, as a
result of the foregoing among other things, the members of IKOS' board breached
their fiduciary duties. The lawsuit alleges that Synopsys aided and abetted the
IKOS board in the alleged breach of their fiduciary duties. The lawsuit seeks
injunctive relief and unspecified damages. The plaintiffs in this action have
proposed its consolidation with certain other purported class actions pending in
the Chancery Court against IKOS and its board; actions in which Synopsys is not
named as a defendant. No date has been set for trial in this matter.

On December 14, 2001, Scott Petler, an alleged stockholder of IKOS, filed
an alleged class action lawsuit in California Superior Court in Santa Clara
County, California (Case No. CV 803814) against IKOS, the members of IKOS' board
of directors, Synopsys and Synopsys Chairman and Chief Executive Officer Aart de
Geus. The lawsuit alleges generally that the members of the IKOS board breached
their fiduciary duties in connection with the Merger Agreement and that Synopsys
and that Dr. de Geus aided and abetted those alleged breaches of fiduciary
duties. The lawsuit seeks a declaration by the Court that IKOS and certain of
its directors and officers entered into the Merger Agreement in breach of their
fiduciary duties. Plaintiffs also seek preliminary and permanent injunctive
relief preventing consummation of the Synopsys-IKOS acquisition as currently
structured. Plaintiffs do not seek monetary damages against Synopsys, Dr. de
Geus, or any other defendant, but do seek costs and disbursements, including
attorneys' and experts' fees.

Synopsys believes that these lawsuits are without merit and intends to
vigorously contest each lawsuit.

The foregoing information is current as of January 7, 2002. Additional
information concerning developments relating to the Merger Agreement and the
litigation matters described above after that date may be disclosed in further
amendments to the Schedule TO of Mentor Graphics and the Schedule 14D-9 of IKOS,
and in filings with the SEC by Synopsys.

There are no other material legal proceedings pending against the Company.

ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS

No matters were submitted for a vote of security holders during the fourth
quarter of the fiscal year covered by this Report.

15

EXECUTIVE OFFICERS OF THE COMPANY

The executive officers of the Company and their ages, as of January 1,
2002, are as follows:

Dr. Aart J. de Geus co-founded Synopsys and currently serves as Chief
Executive Officer and Chairman of the Board of Directors. Since the inception of
Synopsys in December 1986, he has held a variety of positions including Senior
Vice President of Engineering and Senior Vice President of Marketing. From 1986
to 1992, Dr. de Geus served as Chairman of the Board. He served as President
from 1992 to 1998. Dr. de Geus has served as Chief Executive Officer since
January 1994 and has held the additional title of Chairman of the Board since
February 1998. He has served as a Director since 1986. From 1982 to 1986, Dr. de
Geus was employed by General Electric Corporation, where he was the Manager of
the Advanced Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E.
from the Swiss Federal Institute of Technology in Lausanne, Switzerland and a
Ph.D. in electrical engineering from Southern Methodist University.

Dr. Chi-Foon Chan joined Synopsys as Vice President of Application
Engineering & Services in May 1990. Since April 1997 he has served as Chief
Operating Officer and since February 1998 he has held the additional title of
President. Dr. Chan also became a Director of the Company in February 1998. From
September 1996 to February 1998 he served as Executive Vice President, Office of
the President. From February 1994 until April 1997 he served as Senior Vice
President, Design Tools Group and from October 1996 until April 1997 as Acting
Senior Vice President, Design Reuse Group. Additionally, he has held the titles
of Vice President, Engineering and General Manager, DesignWare Operations and
Senior Vice President, Worldwide Field Organization. From March 1987 to May
1990, Dr. Chan was employed by NEC Electronics, where his last position was
General Manager, Microprocessor Division. From 1977 to 1987, Dr. Chan held a
number of senior engineering positions at Intel Corporation. Dr. Chan holds an
M.S. and Ph.D. in computer engineering from Case Western Reserve University.

Vicki L. Andrews joined Synopsys in May 1993 and currently serves as Senior
Vice President, Worldwide Sales. Before holding that position, she served in a
number of senior sales roles at Synopsys, including Vice President, Global and
Strategic Sales, Vice President, North America Sales and Director, Western
United States Sales. She has more than 18 years of experience in the EDA
industry. Ms. Andrews holds a B.S. in biology and chemistry from the University
of Miami.

Robert B. "Brad" Henske joined Synopsys in May 2000 and currently serves as
Senior Vice President and Chief Financial Officer. Mr. Henske joined Synopsys
from Oak Hill Capital Management, a Robert M. Bass Group private equity
investment firm where he was a partner from January 1997 to April 2000.
Additionally, Mr. Henske was Executive Vice President and Chief Financial
Officer, and a member of the board of directors of American Savings Bank, F.A.,
a Bass portfolio company, from January 1996 to December 1996. Prior to that, he
was a business strategy and financial consultant for Bain & Company from
September 1988 to December 1995, where he last held the position of Vice
President. Mr. Henske received an MBA in finance and strategic management from
The Wharton School, University of Pennsylvania. He has served on the board of
directors for several companies, including Grove Worldwide, L.L.C., Williams
Scotsman, Inc., Reliant Building Products, Inc. and American Savings Bank, F.A.

16

Steven K. Shevick joined Synopsys in July 1995 and currently serves as Vice
President, Investor Relations and Legal, General Counsel and Corporate
Secretary. From July 1995 to March 1998 he served as Deputy General Counsel and
Assistant Corporate Secretary. In March 1998 he was appointed Vice President,
Legal and General Counsel. In October 1999, Mr. Shevick gained the additional
title of Vice President of Investor Relations and was appointed Corporate
Secretary. Prior to joining Synopsys, Mr. Shevick was a lawyer in the New York,
Hong Kong and Washington, D.C. offices of Cleary, Gottlieb, Steen & Hamilton,
where his practice focused on international securities transactions, mergers and
acquisitions and technology licensing. Mr. Shevick holds an A.B. from Harvard
College and a J.D. from Georgetown University Law Center.

There are no family relationships among any executive officers of the
Company.

PART II

ITEM 5. MARKET FOR REGISTRANT'S COMMON EQUITY AND RELATED STOCKHOLDER MATTERS

The information required by this item is set forth on page 64 of this
Synopsys 2001 Annual Report on Form 10-K.

ITEM 6. SELECTED FINANCIAL DATA

FINANCIAL SUMMARY

- ---------------

(1) Amounts and per share data for periods presented have been retroactively
restated to reflect the mergers accounted for under the pooling-of interests
method with Viewlogic Systems, Inc, effective December 4, 1997, and Everest
Automation, Inc., effective November 21, 1998.

(2) Synopsys has a fiscal year that ends on the Saturday nearest October 31.
Fiscal years 2000, 1999 and 1997 were 52-week years while fiscal years 2001
and 1998 were 53-week years. Fiscal year 2002 will be a 52-week year. For
presentation purposes, the consolidated financial statements refer to the
calendar month end. Prior to fiscal year 2000, Synopsys' fiscal year ended
on the Saturday nearest to September 30. The period from October 1, 1999
through October 31, 1999 was a transition period. During the transition
period, revenue, loss before income taxes, benefit for income taxes and net
loss were $23.2 million, $25.5 million, $9.9 million, and $15.5 million,
respectively, and basic and diluted loss per share was $0.22. The net loss
during the transition period is due to the fact that sales in the first
month following a quarter end are historically weak. As of October 31, 1999,
working capital, total assets, long-

17

term debt, and stockholders' equity were $621.9 million, $1.2 billion, $11.3
million and $872.6 million, respectively.

(3) Includes charges of $1.7 million, $21.2 million, $33.1 million, $5.5
million, for the fiscal years ended October 31, 2000 and September 30, 1999,
1998, and 1997, respectively, for in-process research and development.
Includes merger-related and other costs of $51.0 million and $11.4 million
for the years ended September 30, 1998 and 1997, respectively.

(4) On October 2, 1998, Synopsys sold a segment of the Viewlogic business for
$51.9 million in cash. As a result of the transaction, Synopsys recorded an
extraordinary gain of $26.5 million, net of income tax expense, in the
fourth quarter of fiscal 1998.

ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND RESULTS
OF OPERATIONS

The following discussion contains forward-looking statements within the
meaning of Section 21E of the Securities Exchange Act of 1934. For example,
statements including terms such as "projects," "expects," "believes,"
"anticipates" or "targets" are forward-looking statements. Actual results could
differ materially from those anticipated in such forward-looking statements as a
result of certain factors, including those set forth under "Factors That May
Affect Future Results."

RESULTS OF OPERATIONS

Introduction of Technology Subscription Licenses (TSLs). On July 31, 2000,
we introduced TSLs, which are time-limited rights to use our software. Since
TSLs include bundled product and services, both product and service revenue is
generally recognized ratably over the term of the license, or, if later, as
payments become due. The terms of TSLs, and the payments due thereon, may be
structured flexibly to meet the needs of the customer. With minor exceptions,
under TSLs, customers cannot obtain major new products developed or acquired
during the term of their license without making an additional purchase. Overall,
we believe that TSLs have enabled us to (i) offer customers technology and terms
that more closely match their needs; (ii) have greater visibility into our
earnings stream; (iii) more effectively resist customer requests for special
end-of-the-quarter discounts; and (iv) roll out our new technologies in a more
planned manner.

The replacement of the prior form of time-based licenses by TSLs has
impacted and will continue to impact our reported revenue. Under a ratable
license, relatively little revenue is recognized during the quarter the product
is delivered. The remaining amount is recorded as deferred revenue to the extent
that the license fee has been paid or invoiced, to be recognized over the term
of the license, or is considered backlog by the Company. This backlog is not
recorded on our balance sheet. Under the prior form of time-based licenses, a
high proportion of all license revenue was recognized in the quarter that the
product was delivered, with relatively little recorded as deferred revenue or as
backlog. Therefore, an order for a TSL will result in significantly lower
current-period revenue than an equal-sized order under the prior form of
time-based license.

We set revenue targets for any given period based, in part, upon an
assumption that we will achieve a certain license mix of perpetual licenses and
TSLs. The actual mix of licenses sold affects the revenue we recognize in the
period. If we are unable to achieve our target license mix, we may not meet our
revenue targets. In fiscal 2001, our license mix for new orders was 80% TSLs and
20% perpetual licenses which is within our targeted range. The average term of
our TSL licenses sold in 2001 was between 3.0 and 3.5 years, which is longer
than expected. Given the difference in the revenue profile of TSLs and perpetual
licenses, this shift in license mix will reduce revenue in the short-term. We
anticipate that our license mix for fiscal 2002 will be approximately 15% to 25%
perpetual licenses and 75% to 85% TSLs.

Business Combinations and Divestitures. On January 4, 2001, we sold the
assets of our silicon libraries business to Artisan Components, Inc. (Artisan)
for a total sales price of $15.5 million, including common stock with a fair
value on the date of sale of $11.4 million, and cash of $4.1 million. The net
book value of the assets sold was $1.4 million. Expenses incurred in connection
with the sale were $3.5 million. We recorded a gain on the sale of the business
of $10.6 million, which is included in other income, net. Direct revenue for the

18

silicon libraries business was $0.2 million, $4.3 million and $10.1 million for
the fiscal years 2001, 2000 and 1999, respectively.

There were no business combinations completed in fiscal 2001.

In fiscal 2000, we acquired (i) VirSim, a software product, from Innoveda,
Inc., for a purchase price of approximately $7.0 million in cash, (ii) The
Silicon Group, Inc., a privately held provider of integrated circuit design and
intellectual property integration services, for a purchase price of $3.0
million, including cash payments of $1.8 million and a reserve of approximately
34,000 shares of common stock for issuance under The Silicon Group's stock
option plan which was assumed in the transaction, and (iii) Leda, S.A. (Leda), a
privately held provider of RTL coding-style-checkers, for a purchase price of
$7.7 million, including cash payments of $7.5 million. Approximately $1.7
million of the Leda purchase price was allocated to in-process research and
development and charged to operations because the acquired technology had not
reached technological feasibility and had no alternative uses. The purchase
price of each of these transactions was allocated to the acquired assets and
liabilities based on their estimated fair values as of the date of the
respective acquisition. Amounts allocated to developed technology, workforce and
goodwill are being amortized on a straight-line basis over periods ranging from
three to five years.

In fiscal 1999, we issued approximately 1.4 million shares of common stock
for all the outstanding stock of Everest, a developer of integrated circuit
routing and related technology, and reserved approximately 120,000 shares of
common stock for issuance under Everest's stock option plan, which we assumed in
the transaction. The business combination was accounted for as a pooling of
interests, and accordingly, our consolidated financial statements have been
restated to include the financial position and results of Everest for all
periods prior to the merger date.

In fiscal 1999, we acquired (i) Gambit Automated Design, Inc. (Gambit), a
privately held provider of place and route software and physical design services
for a purchase price of $41.3 million including, $29.2 million in cash, $8.0
million in notes payable and a reserve of approximately 78,000 shares of common
stock for issuance under Gambit's stock option plan which was assumed in the
transaction, (ii) Stanza Systems, Inc. (Stanza), a privately held company with
physical layout editor expertise and technology for a purchase price of $15.4
million including, $11.0 million in cash, the issuance of approximately 46,000
shares of common stock and a reserve of approximately 21,000 shares of common
stock for issuance under Stanza's stock option plan which was assumed in the
transaction, (iii) Smartech OY, a privately held design services firm with
expertise in the design of wireless communication devices for a purchase price
of approximately $9.7 million in cash, (iv) the rights to CoverMeter, a Verilog
code coverage tool, from Advanced Technology Center of Massachusetts
(CoverMeter) for a purchase price of $4.5 million including $2.3 million in cash
and $2.2 million of notes payable, and (v) Apteq, Inc. (Apteq) which has an
expertise in analog simulation and Verilog-A product for a purchase price of
$2.0 million including $1.0 million in cash, notes payable of $0.6 million and
$0.4 million in the assumption of debt. Amounts allocated to in-process research
and development and charged to operations because the acquired technology had
not reached technological feasibility and had no alternative future uses were
(i) $13.9 million for Gambit (ii) $4.1 million for Stanza, (iii) $2.4 million
for CoverMeter and (iv) $0.8 million for Apteq. The purchase price of each of
the transactions was allocated to the acquired assets and liabilities based on
their estimated fair values as of the date of the respective acquisition.
Amounts allocated to developed technology, workforce and goodwill are being
amortized on a straight-line basis over periods ranging from three to five
years.

Revenue. Revenue consists of fees for perpetual and ratable licenses of
the Company's software products, sales of hardware system products,
post-contract customer support (PCS), customer training and consulting. We
classify revenues as product, service or ratable license. Product revenue
consists primarily of perpetual and non-ratable time-based license revenue.
Service revenue consists of PCS under perpetual and non-ratable time-based
licenses and fees for consulting services and training. Ratable license revenue
consists of revenue from TSLs and from time-based licenses that include extended
payment terms or unspecified additional products.

Revenue for fiscal 2001 decreased 13% to $680.4 million, as compared to
$783.8 million for fiscal 2000, consistent with our expectations. The decrease
in revenue in 2001 compared to 2000 is due to the utilization
19

for the full 2001 fiscal year of the ratable license model and the related
inherent decrease in revenue due to the timing of revenue recognition under this
license model.

Product revenue decreased by 62% to $163.9 million in fiscal 2001 from
$434.1 million in fiscal 2000 and decreased by 14% from $505.8 million in fiscal
1999 compared to fiscal 2000. The decrease in fiscal 2001 and fiscal 2000 is
primarily due to the change in the license model to TSLs, for which revenue is
recognized ratably over the term of the license.

Service revenue consists of consulting revenue, training and PCS on
perpetual licenses. Service revenue remained relatively flat at $341.8 million
in fiscal 2001 compared to $340.8 million in fiscal 2000. Service revenue in the
first half of fiscal 2001 was $178.5 million, compared to $168.1 million for the
same period in fiscal 2000. This 6% increase was a result of increased sales of
our turnkey design and wireless and broadband consulting services. However, full
fiscal year 2001 services revenue was impacted by cost-cutting efforts by
customers during the second half of the fiscal year, which led to rescheduling
of delivery dates on certain consulting projects and cancellation of others. As
a result, projects anticipated to produce revenue in the second half of fiscal
2001 were not completed. Assuming no improvement in the current economic
climate, the Company anticipates that customers will continue to review their
engagements with outside consultants, and may eliminate or defer those
determined to be non-critical. During fiscal 2000, service revenue increased by
13% from $300.3 million in fiscal 1999 compared to fiscal 2000. This increase
was primarily attributable to the renewal of maintenance and support contracts
for EDA products and growth in customer training and consulting services.

Over time, service revenue will be impacted by three trends. First, new
licenses are increasingly structured as TSLs including the bundled PCS. Second,
customers with existing perpetual licenses are increasingly entering into new
TSLs rather than renewing the PCS on the existing perpetual license. Third,
customers with existing perpetual licenses are increasingly converting their
existing licenses to TSLs. Each of these trends will result, over time, in lower
service revenue.

Ratable license revenue was $174.6 million for fiscal 2001 and $8.9 million
for fiscal 2000. During fiscal 2001, ratable revenue equaled $31.0 million,
$38.9 million, $49.8 million and $54.9 million for the first, second, third and
fourth quarters of 2001, respectively, increasing on a sequential quarter basis
in each quarter of the year. We expect sequential increases to continue through
fiscal 2002.

International Revenue. The following table summarizes the performance of
the various geographic regions as a percent of total Company revenue:

Revenue from international operations was $253.9 million, $327.0 million
and $275.2 million, or 37%, 42% and 34% of total revenue in fiscal 2001, 2000
and 1999, respectively. In any given period, the geographic mix of revenue is
influenced by the particular contracts closed during that quarter, although the
fluctuation on geographical mix should become less pronounced as the ratable
revenue model continues to phase in. The decline in international revenues from
fiscal 2000 to fiscal 2001 is due to a decline in the revenue contribution from
Japan. The increase in international revenue as a percentage of total revenue in
fiscal 2000 compared to fiscal 1999 was primarily a result of relatively greater
revenue growth in Japan.

Revenue Expectations. During fiscal 2002, we expect revenue to consist of
approximately 20% perpetual licenses, 40% TSLs and 40% services. Due to the
current economic environment, we do not currently have sufficient visibility
into revenues for the full fiscal 2002 year to be able to forecast such full
year revenues with
20

a reasonable accuracy. These expectations do not take into account the potential
impact of the proposed mergers with Avant!, Inc. and IKOS Systems, Inc.

Revenue -- Product Groups. For management reporting purposes, our products
have been organized into four distinct product groups -- IC Implementation,
Verification and Test, Intellectual Property (IP) and System Level Design,
Transistor Level Design -- and a services group -- Professional Services. The
following table summarizes the revenue attributable to the various groups and as
a percentage of total Company revenue since the introduction of the ratable
license model:

IC Implementation. IC implementation includes two product categories, the
Design Compiler (DC) Family and Physical Synthesis. The DC Family includes
Design Compiler, our core logic synthesis product, Power Compiler, which permits
optimization of the design of low power circuits, and Module Compiler, which is
used in the design of complex datapaths.

Quarterly revenue from the DC Family has increased since the introduction
of our ratable license model, from $44.7 million in the fourth quarter of 2000
to $58.0 million in the fourth quarter of 2001. This increase is driven by a
continued increase in revenues from Design Compiler. As a percentage of total
revenue, the DC Family has remained relatively flat over the last five quarters,
ranging from 32% to 34%. While we expect the relative revenue contribution from
the DC Family to decline over time as our customers transition from the DC
Family products to Physical Synthesis products, Design Compiler remains one of
our top-selling products.

Included in the Physical Synthesis family is Physical Compiler, a product
that unifies synthesis, placement and global routing, Chip Architect, a chip
floor-planning product, and our detailed routing technology. During the fourth
quarter of 2001, we announced our Route Compiler and ClockTree Compiler
products. Quarterly revenue from this product family has increased sequentially
over the last five quarters with the exception of the first quarter of 2001. The
overall increase in quarterly sales is related primarily to an increase in
revenues from Physical Compiler. The decrease in revenue in the first quarter of
2001 compared to the fourth quarter of 2000 is due to the mix of license types
sold in the quarter; specifically, fewer perpetual licenses were sold in that
quarter compared to the preceding and following quarters.

Verification and Test. Verification and Test includes our simulation,
timing analysis, formal verification and test products. Revenue has increased in
each quarter since the introduction of our ratable license model. These
sequential increases are primarily due to growth in revenue for our Verilog
simulator, VCS and Prime Time.

Intellectual Property (IP) and Systems Products. Our IP and Systems
Products Group includes the DesignWare library of design components and
verification models, and system design products. Revenue increased sequentially
from the fourth quarter of fiscal 2000 through the third quarter of fiscal 2001,
primarily due to increased DesignWare revenue. In the first quarter of fiscal
2001, we sold our silicon libraries business, which contributed direct revenue
of $0.2 million and $0.5 million, in the first quarter of fiscal 2001 and the

21

fourth quarter of fiscal 2000, respectively. During the fourth quarter of fiscal
2001, there was a decrease in revenue as compared to the third quarter of fiscal
2001 from our DesignWare product of approximately $1.0 million due to an
increase in the average term of the subscription or ratable licenses in fiscal
2001 in comparison to fiscal 2000. During the fourth quarter of fiscal 2001, we
also discontinued our Eagle product, which in fiscal 2001 and 2000 contributed
direct revenue of $2.4 million and $3.3 million, respectively.

Transistor Level Design. Our transistor level design product group
includes tools that are used in transistor-level simulation and analysis.
Revenue in total, and as a percent of total Company revenue, from this product
group has fluctuated since the introduction of TSLs as a result of the mix of
license types of orders received. The decline in the fourth quarter is due
primarily to an increase in the percentage of ratable licenses during the fourth
quarter as compared to the third quarter.

Professional Services. The Professional Services group includes consulting
and training. This group provides consulting services, including design
methodology assistance, specialized telecommunications systems design services
and turnkey design. Revenue from professional services increased quarterly from
the fourth quarter of 2000 through the second quarter of 2001 as a result of
increased sales of our turnkey design and wireless and broadband consulting
services. However, in the third quarter of 2001, revenue from professional
services declined 23% in comparison to the previous quarter and decreased an
additional 3% in the fourth quarter of 2001, as compared to the third quarter.
These decreases in service revenue in the second half of fiscal 2001 are the
result of certain consulting projects, which were not completed as delivery
dates were pushed out to future periods or canceled by customers. This was
caused by the tightening economy. Due to the current economic climate, customers
may continue to reduce costs, cancel orders or extend the delivery dates on
existing purchase orders.

Cost of Revenue. Cost of product revenue includes personnel and related
costs, production costs, product packaging, documentation, amortization of
capitalized software development costs and purchased technology, and costs of
the components of the our hardware system products. The cost of internally
developed capitalized software is amortized based on the greater of the ratio of
current product revenue to the total of current and anticipated product revenue
or the straight-line method over the software's estimated economic life of
approximately two years. Cost of product revenue was 12% of total product
revenue for fiscal 2001, as compared to 8% for fiscal 2000. This increase in
cost of product revenue as a percentage of total product revenue is due
primarily to the write-off of certain Eagle intangible assets totaling $1.8
million and an increase in the inventory reserve totaling $1.3 million related
to our hardware modeling product because we are transitioning customers to the
next generation product. The Company's product costs are relatively fixed and do
not fluctuate significantly with changes in revenue or changes in revenue
recognition methods. Cost of product revenue was 7% of total product revenue for
fiscal 1999.

Cost of service revenue includes consulting services, personnel and the
related costs associated with providing training, and PCS on perpetual licenses.
Cost of service revenue as a percentage of total service revenue has remained
relatively flat at 23% in fiscal 2001, 24% in fiscal 2000 and 23% in 1999.

Since TSLs include bundled product and services, cost of ratable license
revenue includes the costs of product and services related to our TSLs. Cost of
ratable license revenue was 17% for fiscal 2001.

Because cost of product and TSL revenue is based on the mix of orders, as
customers migrate to the TSL model, cost of product revenue will decrease as a
percentage of total revenues. Over time, as more TSL deferred revenue is
amortized, cost of TSL revenue will also decrease as a percentage of revenue.
During fiscal 2002, we expect that the cost of product revenue as a percent of
total product revenue will remain flat and the cost of TSL revenue as a percent
of total TSL revenue will either remain flat or decrease slightly. The cost of
service revenue as a percent of the related revenue is also expected to remain
relatively flat or decrease slightly.

Research and Development. Research and development expenses, net of
capitalized software development costs, in terms of annual spending, remained
relatively flat at $189.8 million in fiscal 2001, compared to $189.3 million in
fiscal 2000, and increased by 13% in fiscal 2000 compared to $167.1 million in
fiscal 1999. The change in absolute dollars between 2001 and 2000 reflects
increases in personnel related costs, recruiting

22

costs and depreciation expense offset by a decrease in facilities due to certain
facilities which were acquired in the Gambit acquisition and closed during the
fourth quarter of fiscal 2000, as well as decreases in equipment repairs,
advertising expenses and travel and entertainment costs. Research and
development expenses represented 28%, 24% and 21% of total revenue in fiscal
2001, 2000 and 1999, respectively. The increase in research and development
expenses as a percentage of total revenue is due to the decrease in total
revenues as a result of a change in our license model. The increase in research
and development spending in fiscal 2000 compared to fiscal 1999 was due
primarily to increases in personnel and related costs as a result of business
combinations and higher levels of research and development staffing in support
of our roll-out of Physical Compiler. In each year, additions of personnel were
made to facilitate the enhancement of existing applications and development of
new products. We believe that to maintain our competitive position in a market
characterized by rapid rates of technological advancement, we must continue to
invest significant resources in new systems and software, and continue to
enhance existing products. We anticipate that we will continue to commit
substantial resources to research and development in the future. If we determine
that we are unable to enter a particular market in a timely manner, we may
license technology from other businesses or acquire other businesses as an
alternative to internal research and development.

Sales and Marketing. Sales and marketing expenses decreased by 5% to
$274.0 million in fiscal 2001 from $288.8 million in fiscal 2000 and increased
by 20% from $241.4 million in fiscal 1999 compared to fiscal 2000. Total
expenses decreased in fiscal 2001 as compared to fiscal 2000 primarily as a
result of decreases in annual bonuses, travel, consulting expenses, recruiting,
advertising and depreciation expense, offset by increases in personnel-related
costs. Sales and marketing expenses represented 40%, 37% and 30% of total
revenue in fiscal 2001, 2000 and 1999, respectively. Sales and marketing
expenses increased as a percentage of total revenue due to a decrease in total
revenue as a result of the change in our license model. Total expenses increased
in absolute dollars in fiscal 2000 compared to fiscal 1999 primarily as a result
of an increase in sales commissions and bonus costs.

General and Administrative. General and administrative expenses increased
18% to $69.7 million in fiscal 2001 compared to $59.2 million in fiscal 2000.
General and administrative expense increased from $47.2 million in fiscal 1999
compared to fiscal 2000. General and administrative expenses increased during
fiscal 2001 due to increases in bad debt expense, facility expenditures and
consulting services related to the upgrade of our current computer systems
offset by a decrease in personnel costs. As a percentage of total revenue,
general and administrative expenses were 10%, 8% and 6% in fiscal 2001, 2000 and
1999, respectively. The increase in general and administrative expenses
increased as a percentage of total revenue due to a decrease in total revenue as
a result of the change to our license model. In fiscal 2000, the increase in
absolute dollars and percentage of revenue compared to fiscal 1999 was primarily
due in part to increases, in order of magnitude, in personnel costs, an increase
in bad debt expense relating to the accounts receivable allowance provided in
accordance with our historical trends, facility expenditures and patent and
proxy services.

Operating Expense Targets -- Fiscal 2002. As a result of our cost-cutting
measures implemented in the fourth quarter of fiscal 2001 and affecting expense
levels in fiscal 2002, we expect that total operating expenses for the full
fiscal year 2002 will be relatively flat compared to fiscal 2001 levels.

Amortization of Intangible Assets. Intangible assets represent the excess
of the aggregate purchase price over the fair value of the tangible assets and
other identifiable intangible assets acquired by the Company (goodwill). Under
our accounting policies, intangible assets as of October 31, 2001, including
goodwill, are being amortized over the estimated useful life of three to five
years. Amortization of intangible assets charged to operations amounted to $17.0
million, $15.1 million and $7.9 million in fiscal 2001, 2000 and 1999,
respectively.

We periodically evaluate our intangible assets for indications of
impairment. If this evaluation indicates that the value of the intangible asset
may be impaired, an evaluation of the recoverability of the net carrying value
of the asset over its remaining useful life is made. If this evaluation
indicates that the intangible asset is not recoverable, based on the estimated
undiscounted future cash flows of the entity or technology acquired over the
remaining amortization period, the net carrying value of the related intangible
asset will be reduced to fair value and the remaining amortization period may be
adjusted. In fiscal 2001, we recognized an aggregate

23

impairment charge of $2.2 million to reduce the amount of certain intangible
assets associated with prior acquisitions to their estimated fair value.
Approximately $1.8 million and $0.4 million are included in cost of revenues and
amortization of intangible assets, respectively, on the statement of operations.
The impairment charge is attributable to certain technology acquired from, and
goodwill related to the acquisition of Eagle Design Automation, Inc. in 1997.
During the fourth quarter of fiscal 2001, we determined that we would not
allocate future resources to assist in the market growth of this technology and
we do not anticipate any future sales of the product. There were no impairments
of intangible assets in fiscal 2000 and 1999.

In-Process Research and Development. The following paragraphs contain
forward-looking statements within the meaning of Section 21E of the Securities
Exchange Act of 1934, including statements and assumptions regarding percentage
of completion, expected product release dates, dates for which we expect to
begin generating benefits from projects, expected product capabilities and
product life cycles, costs and efforts to complete projects, growth rates,
royalty rates and projected revenue and expense information used by us to
calculate discounted cash flows and discount rates. These forward-looking
statements involve risks and uncertainties, and the cautionary statements set
forth below and in "Factors that May Affect Future Results" identify important
factors that could cause actual results to differ materially from those
predicted in any such forward-looking statement.

Purchased in-process research and development (IPRD) of $1.7 million and
$21.2 million in fiscal 2000 and 1999 respectively, represent the write-off of
in-process technologies associated with our acquisitions of Leda in fiscal 2000
and Gambit, Stanza, CoverMeter, and Apteq, in fiscal 1999. At the date of each
acquisition the projects associated with the IPRD efforts had not yet reached
technological feasibility and the research and development in process had no
alternative future uses. Accordingly, these amounts were expensed on the
respective acquisition dates of each of the acquired companies. (Also see Note
3, Business Combinations, of Notes to Synopsys' Consolidated Financial
Statements.)

Valuation of IPRD. We calculated amounts allocated to IPRD using
established valuation techniques in the high technology industry and expensed
such amounts in the quarter that each acquisition was consummated because
technological feasibility had not been achieved and no alternative future uses
had been identified. In each of the acquisitions that had associated significant
IPRD charges during fiscal 2000 and 1999, the valuation of IPRD was determined
as discussed in the next three paragraphs. Information specific to the
significant IPRD charges in 2000 and 1999 follows.

The value assigned to acquired in-process technology was determined by
identifying products under research in areas for which technological feasibility
had not been established. The value of in-process technology was then segmented
into two classifications: (i) in-process technology -- completed and (ii) in-
process technology -- to-be-completed, giving explicit consideration to the
value created by the research and development efforts of the acquired business
prior to the date of acquisition and to be created by Synopsys after the
acquisition. These value creation efforts were estimated by considering the
following major factors: (i) time-based data, (ii) cost-based data and (iii)
complexity-based data.

The value of the in-process technology was determined using a discounted
cash flow model similar to the income approach, focusing on the income-producing
capabilities of the in-process technologies. Under this approach, the value is
determined by estimating the revenue contribution generated by each of the
identified products within the classification segments. Revenue estimates were
based on (i) individual product revenues, (ii) anticipated growth rates (iii)
anticipated product development and introduction schedules (iv) product sales
cycles, and (v) the estimated life of a product's underlying technology. From
the revenue estimates, operating expense estimates, including costs of sales,
general and administrative, selling and marketing, income taxes and a use charge
for contributory assets, were deducted to arrive at operating income. Revenue
growth rates were estimated by management for each product and gave
consideration to relevant market sizes and growth factors, expected industry
trends, the anticipated nature and timing of new product introductions by us and
our competitors, individual product sales cycles, and the estimated life of each
product's underlying technology. Operating expense estimates reflect our
historical expense ratios. Additionally, these projects will require continued
research and development after they have reached a state of technological and
commercial feasibility. The resulting operating income stream was discounted to
reflect its present value at the date of the

24

acquisition. These estimates are subject to change, given the uncertainties of
the development process, and no assurance can be given that deviations from
these estimates will not occur or that we will realize any anticipated benefits
of the acquisition.

The rate used to discount the net cash flows from purchased in-process
technology is our weighted average cost of capital (WACC), taking into account
our required rates of return from investments in various areas of the
enterprise, and reflecting the inherent uncertainties in future revenue
estimates from technology investments including the uncertainty surrounding the
successful development of the acquired in-process technology, the useful life of
such technology, the profitability levels of such technology, if any, and the
uncertainty of technological advances, all of which are unknown at this time.

Gambit. In March 1999, the Company acquired Gambit. Upon consummation of
the Gambit acquisition, we immediately recognized expense of $13.9 million
representing the acquired in-process technology that had not yet reached
technological feasibility and had no alternative future use. At the date of the
acquisition, the principal in-process technologies identified were Gambit's
integrated circuit routing and clock tree synthesis (CTS) technologies, both of
which are related to the physical design of integrated circuits. For purposes of
valuing the IPRD in accordance with the methodology discussed above, the
following estimates were used: revenue growth ranging from 57% in year two to 9%
in year five; cost of sales -- 20% of revenue in each year; general and
administrative expenses -- 18% of revenue in each year; and sales and
marketing -- 21% of revenue in each year. In addition, it was assumed there
would be no expense reduction due to economic synergies as a result of the
acquisition. The rate used to discount the net cash flows from the Gambit
purchased in-process technology was 25%. The technologies were approximately 75%
complete at the acquisition date. The nature of the efforts to complete these
projects related, in varying degrees, to the completion of all planning,
designing, prototyping, verification, and testing activities that are necessary
to establish that the proposed technologies met their design specifications,
including functional, technical, and economic performance requirements. The
acquired in-process technologies were originally anticipated to become
commercially viable in fiscal 1999 and 2000. Expenditures to complete the
acquired in-process technologies were expected to total approximately $3.2
million.

Subsequent to the date of the acquisition, we determined that the
in-process technologies acquired would be more commercially viable if they were
integrated with our existing products and technologies in development. Our
decision to integrate the acquired in-process technologies rather than selling
them as stand alone products is the result of changes in technology in the
industry, development of our strategy for entering the market for physical
design software, and market forces. We have incurred research and development
expenses of approximately $8.4 million directly related to the acquired and
enhanced technologies. We introduced routing and CTS products integrating the
acquired in-process technology to a limited number of customers in fiscal 2001
and expect general release of these products in fiscal 2002. The anticipated
incremental revenue contribution from the enhanced technology and the related
costs including cost of sales and incremental general and administrative and
sales and marketing costs, are being evaluated based on current customer
analysis; however, we expect the revenue and the costs related to this product
to be consistent with the valuation assumptions noted above.

The risks associated with this research and development are still
considered high and no assurance can be made that these products will meet
market expectations. If these projects are not successfully developed, future
revenue, and profitability of the acquired Gambit business may be materially
adversely affected. Additionally, the value of other intangible assets acquired
may become impaired. As evidenced by its continued support for these projects,
management believes that we will successfully complete each of the major Gambit
research and development programs.

We obtained a second in-process routing technology from Gambit; this
technology has not been further developed except to the extent necessary to
service former Gambit customers using prior versions of the technology. The
post-acquisition research and development costs have not been materially in
excess of those anticipated at the acquisition date.

During fiscal 2000 and 1999, we made other acquisitions resulting in
aggregate IPRD charges of $1.7 million and $7.3 million, respectively, none of
which were individually material to the results of our
25

operations in the respective year. The fair value of the related IPRD was
determined in a manner substantially similar to that described for Gambit. The
risks associated with this acquired research and development are considered high
and no assurance can be made that these products will generate any benefit to us
or meet market expectations.

Other Income, Net. Other income, net was $83.8 million, $40.8 million and
$37.0 million, or 12%, 5% and 5% of total revenue in fiscal 2001, 2000 and 1999,
respectively. The increase for fiscal 2001 is due in part to an increase in
realized gains on investments, which were $55.3 million for fiscal 2001 as
compared to $13.0 million for fiscal 2000, in part to the receipt of rental
income of $8.6 million in fiscal 2001, as compared to zero for fiscal 2000 and
in part to the gain of $10.6 million on the sale of our silicon libraries
business to Artisan. These gains were partially offset by the write-down of
certain assets in our venture portfolio in the amount of $5.8 million for fiscal
2001 and a lower level of interest income in fiscal 2001 of $12.8 million
compared to $28.1 million in fiscal 2000. The decrease in interest income
primarily reflects our lower average cash balances, which resulted from the
continuation of our stock repurchase programs and the decision to grant extended
payment terms on more revenue contracts in fiscal 2001. Other income, net
increased from fiscal 1999 to fiscal 2000 from a higher mix of higher yield
taxable to tax-exempt investments in fiscal 2000. In addition, in fiscal 2000,
other income, net increased in comparison to fiscal 1999 due to gains realized
on sales of equity investments.

For fiscal 2002, we expect other income and expense to be between $27
million and $33 million, including approximately $16 million from the sale of
investments held by the Company.

During the year ended October 31, 2001, we determined that certain of the
assets held in our venture fund, with an aggregate value of $9.4 million, were
impaired, and that the impairment was other than temporary. Accordingly, we
recorded a charge of approximately $5.8 million to write down the carrying value
of the investments. The impairment charge is included in other income, net. The
impairment charge relates to certain investments in non-public companies and
represents management's estimate of the impairment incurred during the period as
a result of specific analysis of each investment, considering the activities of
and events occurring at each of the underlying portfolio companies during the
quarter. Our portfolio companies operate in industries that are rapidly evolving
and extremely competitive. For equity investments in non-public companies for
which there is not a market in which their value is readily determinable, we
review each investment for indicators of impairment on a quarterly basis based,
primarily on achievement of business plan objectives and current market
conditions, among other factors. The primary business plan objectives we
consider include, among others, those related to financial performance such as
achievement of planned financial results or completion of capital raising
activities, and those that are not primarily financial in nature such as the
introduction of technology or the hiring of key employees on a timely basis. If
it is determined that an impairment has occurred with respect to an investment
in a portfolio company, in the absence of quantitative valuation metrics,
management estimates the impairment and/or the net realizable value of the
portfolio investment based on public- and private-company market comparable
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